Master of Science / Department of Electrical and Computer Engineering / Don M. Gruenbacher / This thesis presents a novel device for delaying Ethernet traffic in a lab setting. Ethernet is the leading standard for communications between computing devices. With the advent of streaming media such as voice over IP phone service and real-time control systems over Ethernet, applications are being rapidly developed that must meet strict communication reliability and timing constraints. Increasingly, these systems must be examined in real world scenarios before actual hardware deployment or protocol release. This increases the demand for both testing equipment and well trained network engineers. Commercial Ethernet delay testing devices are expensive, hardware specific, and not flexible enough for educational purposes. These short-comings make it necessary to design a robust Field Programmable Gate Array (FPGA) based Ethernet delay device that is up to the rigor of educational and research settings. Our approach is based on the inexpensive, high performance Altera Stratix II GX PCI Express development board which can easily be adapted for different delay scenarios. The system's FPGA hardware was developed in Verilog, an industry standard hardware description language, so users will be able to quickly learn, adapt and operate the system. Software for the system's soft processor was developed in C. The device provides a wide range of packet delay from nearly zero up to over fifty milliseconds, as well as providing an easy to use interface with on-the-fly variable delay adjustment. Theoretical throughput was up to 1Gb/s; skew and jitter measurements were comparable with common network switches. These properties allow the device to provide an easy-to-use, inexpensive method to delay Ethernet traffic in lab settings and the device also creates a starting point for future students and researchers to develop high speed traffic delay testbeds. Future work will include 10Gb/s throughput, additional memory capacity and additional software implemented delay profiles.

ITC/USA 2006 Conference Proceedings / The Forty-Second Annual International Telemetering Conference and Technical Exhibition / October 23-26, 2006 / Town and Country Resort & Convention Center, San Diego, California / CTEIP has launched the integrated Network Enhanced Telemetry (iNET) project to foster advances in networking and telemetry technology to meet emerging needs of major test programs as well as within the Major Range and Test Facility Base’s. This paper describes one objective of the vNET concept demonstration to provide a test vehicle instrumentation network architecture that can support additional capabilities for data access to the test vehicle. Specifically, this paper addresses the expansion of the current concept demonstration with the incorporation of the IEEE- 1588 standard as the basis for a network time distribution mechanism. Near-term network-based data acquisition systems will likely consist of a mix of standard IRIG 106 timekeeping and IEEE- 1588 timekeeping; in this paper we will examine the ramifications of using the two approaches with the same test vehicle instrumentation system.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / The adoption of commercial off the shelf networks, such as Ethernet, FireWire and FibreChannel, within the avionics community has dramatically changed the architecture of avionics busses and instrumentation networks. Higher bandwidth links and unified interconnects simplify existing infrastructure and wiring. But due to their point-to-point nature, networking topologies are fundamentally different from systems built on legacy bus technologies such as CAIS and MIL-STD-1553. Switched networks and ring topologies pose various challenges for the implementation of network monitoring hardware, and affect the design of bus monitors and distributed data acquisition systems. This paper discusses some of these issues. In particular we address deployment issues, architectural choices such as pass-through versus tap approach, as well as handling of bandwidth requirements and complex communication protocols. We illustrate on the basis of a FireWire monitoring system how these obstacles have been overcome for one given application.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The technologies used for flight test are evolving. Trusted standards like CAIS and IRIG106 PCM are giving way to new “trusted standards” (and proven technologies/protocols) found in telecommunication and networking such as Ethernet, fiber channel, TCP/IP, UDP, ATM and so on. Currently there is $100Ms+ invested in CAIS and IRIG compliant equipment in the world. A key challenge in this evolution is to provide a reliable solution that allows the FTI engineer to immediately take advantage of these advanced technologies while protecting prior investment in equipment, knowledge, and resources during this transition. This paper presents an analysis of how to protect existing assets while still leveraging the power of the latest technologies. It looks at the characteristics of a “bridge” system, and suggests solutions for merging and linking data from and to different transmission protocols using data synchronization and deterministic data management cycles.

ITC/USA 2008 Conference Proceedings / The Forty-Fourth Annual International Telemetering Conference and Technical Exhibition / October 27-30, 2008 / Town and Country Resort & Convention Center, San Diego, California / Synchronization of the iNET communication link is essential for implementing the TDMA channel access control functions within the transceiver MAC transport layer, and providing coherent signal demodulation timing at the transceiver PHY layer. In the following implementation, the 1588 timing reference source is the GPS receiver. Because it is being used in the Ground Station Segment and Test Article Segment, it becomes feasible to utilize the 1588 timing reference for cross-layer (MAC+PHY) iNET transceiver synchronization. In this paper, we propose an unified iNET transceiver synchronization architecture to improve iNET transceiver performance. The results of the synchronization performance analysis are given.

ITC/USA 2008 Conference Proceedings / The Forty-Fourth Annual International Telemetering Conference and Technical Exhibition / October 27-30, 2008 / Town and Country Resort & Convention Center, San Diego, California / Unlike communications protocols that are bus-based or multi-drop (e.g., CAIS Bus, Fibre Channel, RS-485), Ethernet relies on a point-to-point connection topology. One reason for this approach is to allow network nodes to negotiate their individual mode of communication with the network, i.e., link speed and duplexity. The goals of this paper are twofold. The first goal is to describe the process of link negotiation between nodes. This will include some of the details of how two physical layer devices establish communication. The second goal is to show how networked data acquisition nodes are physically connected within the overall system.

ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada / The development of network-based data acquisition systems has resulted in a new architecture for supporting flight instrumentation that has the potential to revolutionize the way we test our aircraft. Unlike conventional flight test instrumentation, networks provide for a two-way communication path between all elements of the system, utilize packetized data, support communication protocols, have dynamic quality of service levels, can be subject to loss of data, utilize asynchronous transmission behavior and provide an even higher level of time synchronization. Different flight test architectures can be realized which combine each of the previous attributes in different ways; finding the best architecture for a set of given applications while minimizing cost and complexity is a very difficult problem. For the last 3 years, the Network Products Division at Teletronics has been involved in the design and evaluation of aircraft instrumentation networks for both customers and the iNET program. This paper describes the result of these efforts by discussing the high-level design of a modular architecture for an aircraft instrumentation network.

International Telemetering Conference Proceedings / November 04-07, 1991 / Riviera Hotel and Convention Center, Las Vegas, Nevada / New techniques for using Ethernet in real time systems are applicable to the typical requirements of high performance Telemetry installations. Most TM installations around the world today are currently implemented using specialized, high speed, point-to-point data paths which have reached their limits in performance. By using Ethernet in real time as a “Data Highway” path, system performance is optimized, and the effective life of a Telemetry system can be significantly extended. Additionally, by integrating a Local Area Network into the system, further advantages are realized. New graphics display hardware and software may be used to provide virtually an “offthe-shelf”, and very cost-effective major system upgrade. Meanwhile, little modification to the host processor hardware or software system is required. This paper examines these premises, and discusses several examples of major Telemetry systems which have made this upgrade.

International Telemetering Conference Proceedings / October 13-16, 1986 / Riviera Hotel, Las Vegas, Nevada / The Experimental Flight Test organization of the Boeing Commercial Airplane Company has an onboard data reduction system known as the Airborne Data Analysis/Monitor System or ADAMS. ADAMS has evolved over the last 11 years from a system built around a single minicomputer to a system using two minicomputers to a distributed processing system based on microprocessors. The system is built around two buses. One bus is used for passing setup and control information between elements of the system. This is burst type data. The second bus is used for passing periodic data between the units. This data originates in the sensors installed by Flight Test or in the Black Boxes on the airplane. These buses interconnect a number of different processors. The Application Processor is the primary data analysis processor in the system. It runs the application programs and drives the display devices. A number of Application Processors may be installed. The File Processor handles the mass storage devices and such common peripheral devices as the printer. The Acquisition Interface Assembly is the entry point for data into ADAMS. It accepts serial PCM data from either the data acquisition system or the tape recorder. This data is then concatenated, converted to engineering units, and passed to the rest of the system for further processing and display. Over 70 programs have been written to support activities on the airplane. Programs exist to aid the instrumentation engineer in preparing the system for flight and to minimize the amount of paper which must be dealt with. Additional programs are used by the analysis engineer to evaluate the aircraft performance in real time. These programs cover the tests from takeoff through cruise testing and aircraft maneuvers to landing. They are used to analyze everything from brake performance to fuel consumption. Using these programs has reduced the amount of data reduction done on the ground and in many cases eliminated it completely.

International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The Western Aeronautical Test Range (WATR) operates the ground stations for research vehicles operating at the NASA Dryden Flight Research Center (DFRC). Recently, the WATR implemented a new system for distributing Time, Space, and Position Information (TSPI) data. The previous system for processing this data was built on archaic hardware that is no longer supported, running legacy software with no upgrade path. The purpose of the Radar Information Processing System (RIPS) is to provide the ability to acquire TSPI data from a variety of sources and process the data for subsequent distribution to other destinations located at the various DFRC facilities. RIPS is built of commercial, off the shelf (COTS) hardware installed in Personal Computers (PC). Data is transported between these computers on a Gigabit Ethernet network. The software was developed using C++ with a modular, object-oriented design approach.