This research presents an analysis of the improvement in the performance of a class of fault tolerant multistage interconnection networks. In the network discussed here, fault tolerance is achieved by providing multiple redundant paths between the source and destination. The extra paths are obtained by providing redundant links between switching elements within a stave (intra-stage links), thereby increasing the switching element complexity. The techniques used in the construction of this network, its properties, advantages, and disadvantages are discussed. While early studies focused their effort in analyzing the fault tolerant characteristics of the network and the performance in a circuit switched environment, this investigation complements the previous work by examining fie performance of a packet switched network. The reasons for the choice of the architecture that include factors like hardware complexity, cost and simplicity of control algorithm are analyzed. The study concentrates on improving the run-time performance of the fault tolerant network. by using these multiple paths not only in the presence of a fault, but also in a fault-free environment. The throughput of the packet switched network in the presence of a fault, congestion and when fault free are analyzed. A description of the investigation, assumptions and factors used for the study, a cost analysis, and the results of the simulation analyses is included. / Master of Science

Microprocessors are used in many applications where a high degree of reliability is required. For instance, satellite based systems operating in space have no way being serviced if something were goes wrong. Often these systems, operating in radiation environments, are subject to random high energy particles that pass through the device and upset the operation of the microprocessor for a short period but leave no permanent damage. These transient faults are difficult to predict, prevent, or detect but can lead to a system failure if not discovered. / Master of Science

An overview of an existing hierarchical reconfiguration scheme for a fault-tolerant two-dimensional cellular architecture is presented, wherein an array of finite state machine cells controls the processing and switching elements. This allows the array to either reconfigure in the presence of faults, or to perform different processing functions. Since the control mechanism is distributed, the system is not subject to single-point "hard core" failures, as in the case of a global control mechanism. Unlike other fault-tolerant systems, the proposed method does not assume the existence of components which never fail. The processing elements in the array are logically connected in a mesh pattern, and are provided with additional physical connections to other cells. A local reconfiguration scheme allows faulty cells to be bypassed via these additional connections, so that the logical mesh can be restored. This technique allows the array to quickly reconfigure in the presence of up to triple faults. When local reconfiguration fails, the array can still reconfigure by using a global reconfiguration scheme, in which the functional part of the array relocates itself to a faultfree area. The process is "global" in the sense that the entire functional part of the array is involved in the process, but the mechanism to accomplish this is still distributed in nature. With the framework of the system established, the results of this research are presented. The hardware complexities of the existing global reconfiguration scheme are analyzed, and compared with the complexities of previous work in this area. A distributed diagnosis algorithm is also developed, which works in conjunction with the local reconfiguration mechanism to quickly detect and isolate faults in the array. Using these results, the foundations are laid for a totally self-checking implementation of the control cells, which allows online concurrent fault detection in the array. / Master of Science

In chip level testing using hardware description language approach, a difficult question to answer is: What is the best micro-operation perturbation for modeling fault at the chip level? In this thesis, an automatic evaluation system is developed to determine the best micro-operation perturbation. The measure used is the gate level stuck-at fault coverage achieved by the tests derived to cover the micro-operation perturbation faults. For small combinational circuits, it is shown that perturbing the elements into the logic dual is a good choice. For large combinational circuits, it is shown that there is very little variation in the gate level coverage achieved by the various microoperation faults. In this case, if coverage is to be improved, the micro-operation perturbation method must be augmented by other techniques. / Master of Science

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 81-85). Available also in a digital version from Dissertation Abstracts.

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D. Tech. Electrical Engineering. / Discusses how to mitigate unnecessary and expensive damage to a power transmission grid, the purpose of this work are therefore: to identify the unique signature of various types of short circuit faults on electric power transmission lines. To formulate mathematical techniques for the characterisation of faults on the electric power transmission grid.To evaluate algorithms that can classify various types of short circuit faults on electric power transmission lines. To develop an ultra fast fault diagnosis system. In addition, this work would make a contribution in the following areas: filtering of decaying DC offset in post fault measurement, formulation of a features extraction algorithm for all short circuit faults on electric transmission lines, evaluation of efficient classiers and regression algorithms, and formulation of faults diagnostic scheme for electric power transmission lines.

No description available.

No description available.