It is important to have the ability to predict the effects of device model variation when designing integrated transconductance-C type active filters. Applying these filters to integrated circuit design has become increasingly popular due to its ease of implementation in monolithic form. With the introduction of fully automated design tools, predictable behavior of high-level variables becomes still more important. The purpose of this study is to evaluate the process parameter spread of analog device models to determine the effect on the design parameters of an active filter. This information's significant contribution directly effects the feasibility and realization of automating analog filter design. In order to explore the dependence of filter performance on the device v model parameter spread, a fifth-order inverse Chebyshev filter is designed and simulated using a two year history of process models. It has not been observed that higher order filters have been successfully designed using fully automated design tools. This filter was realized using automated filter design currently being developed in parallel with this study. A single-ended input to single-ended output transconductance amplifier is chosen for this design for its simplicity and small size. Differential performance is easily adapted with exact duplication which is demonstrated in the measurements of the fabricated filter. Simulation of the design is performed using MOSIS SCNA device parameters. Filter performance data such as cutoff frequency, stopband attenuation, and phase response is collected. Experimental results from the fabricated device are compared to simulation and the original prototype. 2 It is shown that the most predicable effect on the design parameters of a filter is caused by the parasitic output conductance parameter g0. This process dependent variable causes both a deviation in the cutoff frequency, and a decrease in the filter quality factor. In addition, it is also shown that the practice employed to predistort for absorption of parasitic capacitors in a MOS technology is a very effective tool in the reduction of capacitive process dependence.n software

The 24-bit Motorola DSP56001 processor will be used in combination with the DSP56ADC16 and the PCM-56 to design a good FIR compensation filter. Our objective is to digitize the input analog signal, and to compensate for the attenuation in the magnitude response of the digital sine wave. Two different experiments will be conducted, a hands on approach, and a simulation program. The first one will be realized directly, using the DSP system. We will determine the magnitude response of the system, and then deduce the coefficients of the FIR sin(x)/x filter. A look up table will store those values which will be fetched by the DSP program. With a minimum set of instructions we will generate a new digital output sequence after a N-point circular convolution is performed. The output signal is a good reconstruction of the input signal at frequencies below 22 Khz. However, a second experiment will be needed to improve this FIR sin(x)/x compensation filter, because we are not able to go beyond a 300-point impulse sequence. After that value (300-point), the time that each value is read and is ready to be processed by the DSP56001 becomes smaller than the time each instruction in the DSP program is executed and written to the PCM-56 via the SSI register. To be able to expand our experiment, we need to write a simulation program. A simulation program of the previous experiment, which take as input the measured magnitude response of the system. The challenge will be to find ways to map the frequency domain, by using the maximum value of each linear convolution sequence, with a finite input sequence. A step by step approach will be drawn until our final objective is reached. Our final step will be, to increase the number of sampling point in the frequency domain and will be to demonstrate that the result of the simulated program value will coincide with our objective, which is to compensate for the attenuation of the magnitude response of the system. By increasing the sampling frequency we will eventually obtain a good compensation filter.

With advancements in CMOS technology, high speed analog circuits that were traditionally implemented with discrete circuit components can now be made monolithically. Antialiasing filters for video signals as well as signal conditioning filters in high speed communication channels are examples of applications where high frequency integrated circuits are now feasible. Transconductance-Capacitor or Gm-C filters are well suited to these applications as they operate in the continuous-time domain and are able to overcome the high-frequency and noise limitations imposed by clocked filter topologies. This thesis covers the design of a programmable fourth-order Chebychev filter with a 50MHz passband using the transconductance-C technique. A previously proposed transconductor based upon a CMOS inverter is used to implement the filter. Since this transconductor has no internal nodes, it can achieve extremely high bandwidths. However, it requires a variable power source for programming. Thus, a wide-band, on-chip, variable-BiCMOS power supply is presented as the method for setting the transconductance. Practical design issues are addressed as well as many methods for compensating non-idealities. Simulations of the filter as well as some parametric measurement of the filter structures are presented. / Graduation date: 1994

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No description available.

This thesis deals with the design, layout, fabrication, testing and characterization of a second-order filter (biquad) using the transconductance-C (gm-C) technique. The biquad was designed to realize the four filter functions - lowpass, highpass, bandpass and notch - by appropriate choice of input and output terminals and element values. The tunable range of frequencies for the biquad was designed to be 18-59MHz. The quality factor of the biquad was designed to be tunable from approximately 1/3 to 3. The filter was designed in LEVEL2 SPICE, laid out using MAGIC, and the circuit was fabricated using MOSIS's 2μm CMOS analog (n-well) process. The circuit board for testing the chip was designed using the PCB design system -PADS-PCB. The chip was tested using the Network Analyzer HP 4195A. The performance of the filter was then compared with the design objectives and simulation results. Both the pole frequency and the quality factor were found to be tunable by the same factor as the design. Noise analysis showed the output noise to be less than -65dB. The notch function could not be experimentally verified due to high sensitivity of this function to component tolerances and process variations. Power dissipation of the filter was found to be 6m W.

No description available.

Low cost bandpass filters (less than $100) at microwave frequencies cannot be purchased commercially. However, such filters are essential in the design of RF circuits in communications and radar equipment. Reliable microstrip band pass filters which provide an accurate filter response at microwave frequencies can be easily fabricated with low cost. Equations concerning the design of coupled microstrips and microstrip filters are published in the literature and were implemented in a design procedure for maximally flat microstrip band pass filters. The published equations were theoretical and had not been extensively compared with experimental data. Thus, this work established an enhanced microstrip filter design procedure based on experimental data, for a wide range of frequencies and dielectric substrates. The result of this work is an enhanced design procedure for microstrip band pass filters. The new procedure includes a correction factor for the length of the filter resonators which which controls the center frequency of the filter. This correction factor has been found from the measured responses of over 60 filters, which were designed with two different circuit board materials, three different substrate thicknesses, and frequencies ranging between 0.9 and 6 GHz. The experimentally determined length correction factor decreases the error in center frequency from ±5.9% down to ±L7% of the desired design frequency for a wide range of filter designs. The improved procedure has been implemented in a personal computer (PC) program which calculates all dimensions necessary to fabricate microstrip band pass filters in the low microwave frequency range. The maximally flat response obtained is accurate and requires very little tuning. Low cost microstrip band pass filters can now be designed and fabricated easily and with greater accuracy at microwave frequencies. This thesis describes the development of the enhanced design procedure and the results of the filters designed with the new procedure. / Master of Science

The thesis covers a series of PC programs that we have written that will enable users to easily design FIR linear phase lowpass digital filters and multistage sampling rate conversion systems. The first program is a rewrite of the McClellanParks computer program with some slight modifications. The second program uses an algorithm proposed by Rabiner that determines the length of a lowpass digital filter. Rabiner used a formula proposed by Herrmann et al. to initially estimate the filter length in his algorithm. The formula, however, assumes unity gain. We present a modification to the formula so that the gain of the filter is normalized to accommodate filters that have a gain greater than one (as in the case of a lowpass filter used in an interpolator). We have also changed the input specifications from digital to analog. Thus, the user supplies the sampling rate, passband frequency, stopband frequency, gain, and the respective maximum band errors. The program converts the specifications to digital. Then, the program iteratively estimates the filter length and interacts with the McClellan-Parks Program to determine the actual filter length that minimizes the maximum band errors. Once the actual length is known, the filter is designed and the filter coefficients may be saved to a file. Another new finding that we present is the condition that determines when to add a lowpass filter to a multistage decimator in order to reduce the total number of filter taps required to implement the system. In a typical example, we achieved a 34% reduction in the total required number of filter taps. The third program is a new program that optimizes the design of a multistage sampling rate conversion system based upon the sum of weighted computational rates and storage requirements. It determines the optimum number of stages and the corresponding upsampling and downsampling factors of each stage of the design. It also determines the length of the required lowpass digital filters using the second program. Quantization of the filter coefficients may have a significant impact on the frequency response. Consequently, we have included a routine within our program that determines the effects of such quantization on the allowable error margins within the passband and stopband. Once the filter coefficients are calculated, they can be saved to files and used in an appropriate implementation. The only requirements of the user are the initial sampling rate, final sampling rate, passband frequency, stopband frequency, corresponding maximum errors for each band, and the weighting factors to determine the optimization factor. We also present another new program that implements a sampling rate conversion from CD (44.1 kHz) to DAT (48 kHz) for digital audio. Using the third program to design the filter coefficients, the fourth program converts an input sequence (either samples of a sine wave or a unit sample sequence) sampled at the lower rate to an output sequence sampled at the higher rate. The frequency response is then plotted and the output block may be saved to a file.