Decision feedback equalization (DFE) is a sampled-data technique used for data recovery in digital communications channels. Multi-level decision feedback equalization (MDFE) has been developed for channels using the 2/3(1,7) RLL code. The optimum detector for a digital communication channel affected by ISI and noise consists of a matched filter, followed by a symbol rate sampler and a maximum likelihood sequence estimator. The optimal detector is unrealizable for saturation recording channels. A compromise structure uses fixed filter types with adjustable parameters. The objective is to maximize the signal-to-noise ratio in order to minimize the error rate. The read-channel waveform is corrupted at sampling instants by noise generated by various sources. We use a continuous-time low-pass filter cascaded with an all-pass filter at the receiver front-end. The low-pass filter band-limits high-frequency noise before sampling, and the all-pass filter equalizes the signal. This thesis examines different structures of the receiver and their optimal parameter placing. A design methodology developed specifically for choosing the poles and zeros location of the linear front-end part of the receiver is presented. It makes use of nonlinear optimization, and a software package written in MATLAB for equalizer computer aided design (CAD) is included in the appendix. The optimization criterion usually mentioned in the literature for digital channel optimal design is the sum of the intersymbol interference and noise. A new objective function is proposed in the thesis, and the error rate probability is shown to decrease by 30%. Issues pertaining to digital simulation of continuous-time systems are discussed. Design results are presented for different receiver structures, and bit error rate simulations are used for design validation. / Graduation date: 1997

No description available.

No description available.

Advancements in the sophistication and complexity of modern electronic systems are creating a need for highly integrated systems with ever higher operational frequencies. The economical demands of these systems dictate that they be implemented using low cost fabrication technologies, such as digital CMOS. One of the major challenges facing circuit designers is the difficulty in implementing high frequency RF analog circuits on these types of technologies. Analog circuits which make use of parasitic-laden components such as inductors are especially difficult to realize. The purpose of this thesis is to investigate the design and application of an optimization tool based on simulated annealing to this type of problem. The goal is to have the optimizer incorporate these unavoidable component parasitics into a design, and thus eliminate any undesirable performance degradation. The optimization technique will be applied to the design of a CMOS RF distributed amplifier. This type of amplifier has a flat gain characteristic over an exceptionally wide bandwidth, and it is heavily reliant on inductive structures. Historically, an amplifier of this type has never been implemented on a standard CMOS process, without the use of bondwire inductances or special processing techniques. However, it will be shown in this thesis that, with the aid of the optimization technique, a distributed amplifier design can be successfully realized on a standard CMOS process. / Graduation date: 1999

This dissertation investigates the constraints which arise when switched-capacitor (SC) delta-sigma modulators are designed for low-voltage operation, targeting also low power dissipation, and proposes methods of improving the performance and optimizing for low power dissipation. This is accomplished by identifying critical elements whose performance can lead to increased power dissipation, as well as the fundamental limitations of available analog circuit techniques. A prototype was designed and fabricated, which reflected these findings, and therefore exhibited good performance and nearly optimum power dissipation. One of the key performance parameters is the dc gain of the amplifier in the first stage; it should be high. This is necessary for high linearity and low quantization noise leakage. In low-voltage operation, it may become impractical to use conventional topologies employing cascoding techniques (e.g., folded-cascode) which provide high gain in one single stage. Rather, cascaded structures have to be used. The disadvantage of the latter is the necessity for frequency compensation which results in increased power dissipation. Hence, another objective of this work is to exploit techniques which compensate for the open-loop gain characteristic of the amplifier (dc gain and nonlinearity), thus permitting the utilization of single-stage low-gain topologies. Predictive correlated double sampling is one of such techniques and is analyzed in detail. / Graduation date: 1998

Mobile device antenna design and isolation technologies are thoroughly investigated in this thesis. The antenna design parameters for mobile devices are quantified using practical restraints by analyzing almost 60 mobile handsets and the effect of materials, human tissue, manufacturing, and antenna type/placement on antenna design and then mapped into Wheeler-space that correlates the spherical wave modes with the antenna performance. The isolation technologies with mutual coupling anti-resonances are unified by a single performance parameter to distinguish them from the more traditional isolation technologies. This unifying performance parameter is the group delay between two antennas where high group delay indicates the presence of a bandstop filter in the form of either a PCB or an antenna modification. This thesis analyzes both PCB and antenna modifications with high group-delay and demonstrates these types of antennas can be placed in close proximity without affecting other performance parameters. It is also shown that both the PCB and antenna modifications contain two isolation methods where each isolation method is a mirror complement of the other method. Some antenna geometries can also increase the mutual coupling in order to improve the antenna performance using a phenomena called over-coupling. These over-coupled antenna systems can result in lower SAR for the cellular antennas and decreased array sizes for NFC/RFID/wireless-power antennas, resulting in better performance of antennas inside mobile devices. / published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

No description available.

by Cheng Wang-tung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 97-99). / Abstracts in English and Chinese. / Abstract --- p.i / 摘要 --- p.i / Acknowledgements --- p.ii / Table of Contents --- p.iii / List of Figures --- p.vii / List of Tables --- p.xi / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivations --- p.1 / Chapter 1.2 --- Objective --- p.4 / Chapter 1.3 --- Outline --- p.4 / Chapter Chapter 2 --- Quadrature ΣΔ Modulator for A/D Conversion --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- Oversampling ΣΔ Converter --- p.6 / Chapter 2.3 --- Theory of ΣΔ modulation --- p.6 / Chapter 2.3.1 --- Quantization noise --- p.7 / Chapter 2.3.2 --- Oversampling --- p.8 / Chapter 2.3.3 --- Noise Shaping --- p.9 / Chapter 2.3.4 --- Performance Parameter --- p.11 / Chapter 2.3.5 --- Circuit Design of ΣΔ modulator --- p.11 / Chapter 2.3.6 --- Case Study --- p.12 / Chapter 2.3.6.1 --- Transfer Function --- p.12 / Chapter 2.3.6.2 --- Noise Analysis of First Order ΣΔ Modulator --- p.13 / Chapter 2.3.6.3 --- Circuit Level Implementation: --- p.14 / Chapter 2.4 --- Choice of Architecture: Lowpass or Bandpass? --- p.15 / Chapter 2.5 --- I/Q Modulation and Image Rejection --- p.18 / Chapter 2.5.1 --- Quadrature signal --- p.18 / Chapter 2.5.2 --- I/Q Modulation --- p.19 / Chapter 2.6 --- Image Rejection in SC ΣΔ Complex Topology --- p.21 / Chapter 2.6.1 --- High Level Simulation --- p.23 / Chapter 2.6.2 --- Discussion --- p.26 / Chapter 2.7 --- Summary --- p.27 / Chapter Chapter 3 --- Capacitor Sharing Architecture --- p.28 / Chapter 3.1 --- Introduction --- p.28 / Chapter 3.2 --- Proposed mismatch free SC complex ΣΔ Modulator --- p.28 / Chapter 3.2.1 --- Principle of Operation --- p.30 / Chapter 3.3 --- Justification of the Proposed Idea --- p.35 / Chapter 3.4 --- Summary --- p.37 / Chapter Chapter 4 --- Transistor Level Circuit Design --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Design of ΣΔ Modulator --- p.39 / Chapter 4.2.1 --- Specification of ΣΔ Modulator --- p.40 / Chapter 4.3 --- Design of Operational Amplifier --- p.45 / Chapter 4.3.1 --- Folded-cascode Operational Amplifier --- p.45 / Chapter 4.3.2 --- Common Mode feedback --- p.47 / Chapter 4.3.3 --- Bias Circuit --- p.49 / Chapter 4.3.4 --- Simulation Results --- p.50 / Chapter 4.4 --- Design of Comparator --- p.54 / Chapter 4.4.1 --- Regenerative Feedback Comparator --- p.54 / Chapter 4.4.2 --- Simulation Results --- p.55 / Chapter 4.5 --- Design of Clock Generator --- p.56 / Chapter 4.5.1 --- Non-Overlapping clock generation --- p.57 / Chapter 4.5.2 --- Simulation Results --- p.58 / Chapter 4.6 --- Simulation Results of ΣΔ Modulator --- p.59 / Chapter 4.7 --- Simulation Results --- p.61 / Chapter 4.7.1 --- Proposed Architecture --- p.62 / Chapter 4.7.2 --- Traditional Architecture --- p.62 / Chapter 4.8 --- Summary --- p.63 / Chapter Chapter 5 --- Layout Considerations and Post-Layout Simulation --- p.65 / Chapter 5.1 --- Introduction --- p.65 / Chapter 5.2 --- Common-Centroid Structure --- p.65 / Chapter 5.3 --- Shielding Technique --- p.67 / Chapter 5.3.1 --- Shielding of device by substrate --- p.67 / Chapter 5.3.2 --- Floor Planning --- p.68 / Chapter 5.4 --- Layout of Power Rail --- p.69 / Chapter 5.5 --- Layout and Post-Layout Simulation of OpAmp --- p.70 / Chapter 5.6 --- Layout and Post-Layout Simulation --- p.74 / Chapter 5.6.1 --- Proposed Architecture --- p.75 / Chapter 5.6.2 --- Traditional Architecture --- p.77 / Chapter 5.7 --- Summary --- p.79 / Chapter Chapter 6 --- Measurement Results --- p.81 / Chapter 6.1 --- Introduction --- p.81 / Chapter 6.2 --- Considerations of PCB Design --- p.82 / Chapter 6.3 --- Measurement Setup --- p.83 / Chapter 6.4 --- Measurement Results --- p.85 / Chapter 6.4.1 --- Measurement Results of Proposed Architecture --- p.85 / Chapter 6.5 --- Summary --- p.92 / Chapter Chapter 7 --- Conclusion --- p.95 / Chapter 7.1 --- Conclusion --- p.95 / Chapter 7.2 --- Future Works --- p.96 / References --- p.97 / Appendix --- p.100 / Chapter A.1 --- Publications --- p.100 / Chapter A.2 --- Schematic of proposed front end --- p.101 / Chapter A.3 --- Schematic of SC ΣΔ modulator --- p.102 / Chapter A.4 --- Schematic of the folded-cascode amplifier --- p.103 / Chapter A.5 --- Schematic of biasing circuit --- p.104 / Chapter A.6 --- Schematic of preamplifier in comparator --- p.105 / Chapter A.7 --- Schematic of latched part in comparator --- p.106 / Chapter A.8 --- Schematic of the clock generator --- p.107

Yim, Ho Yan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 125-128). / Abstracts in English and Chinese. / Abstract --- p.ii / 論文摘要 --- p.iv / Acknowledgement --- p.vi / Table of Content --- p.vii / List of Figures --- p.x / List of Tables --- p.xiv / Chapter Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Filter --- p.3 / Chapter 1.2 --- Antenna --- p.4 / Chapter 1.3 --- Outline of the Thesis --- p.6 / Chapter Chapter 2 --- Basic Theories in Filter and Patch Antenna Design --- p.7 / Chapter 2.1 --- Microwave Filter Design --- p.7 / Chapter 2.1.1 --- Transfer Functions --- p.8 / Chapter 2.1.2 --- Lowpass Prototype Filters and Elements --- p.14 / Chapter 2.1.3 --- Filter Transformations --- p.18 / Chapter 2.1.4 --- Admittance Inverter --- p.21 / Chapter 2.2 --- Antenna Concepts --- p.23 / Chapter 2.2.1 --- Microstrip Antenna --- p.23 / Chapter 2.2.2 --- Patch Antenna Design --- p.24 / Chapter 2.2.3 --- Polarization --- p.28 / Chapter Chapter 3 --- Review of Conventional Dual-band Filter Designs --- p.33 / Chapter 3.1 --- Bandstop / bandpass Filters in a Cascade Connection --- p.33 / Chapter 3.2 --- Stepped Impedance Resonator --- p.34 / Chapter 3.3 --- Tunable Transmission Zero for Spurious Responses Suppression --- p.36 / Chapter 3.4 --- Comparison --- p.38 / Chapter Chapter 4 --- Novel Dual-band Filter Design with Equal Bandwidth --- p.39 / Chapter 4.1 --- Introduction --- p.39 / Chapter 4.2 --- Frequency Behavior of Shunt Stubs --- p.39 / Chapter 4.3 --- Dual-band Resonator with Paralleled Stubs --- p.42 / Chapter 4.4 --- Dual-band Admittance Inverter --- p.47 / Chapter 4.5 --- Dual-band Filter Realization --- p.51 / Chapter 4.5.1 --- Simulation Examples --- p.54 / Chapter 4.5.2 --- Comparison of Simulation results --- p.60 / Chapter 4.5.3 --- Experimental Results --- p.64 / Chapter Chapter 5 --- Novel Dual-band Filter Design with Unequal Bandwidth --- p.70 / Chapter 5.1 --- Introduction --- p.70 / Chapter 5.2 --- Dual-band Resonator using Step-Impedance Line --- p.70 / Chapter 5.3 --- Dual-band Admittance Inverter --- p.74 / Chapter 5.4 --- Dual-band Filter Realization --- p.75 / Chapter 5.4.1 --- Comparison of Simulation Results --- p.81 / Chapter 5.4.2 --- Experimental Results --- p.85 / Chapter Chapter 6 --- Review of Conventional CP Antenna Designs --- p.91 / Chapter 6.1 --- Degenerated Mode Patch --- p.91 / Chapter 6.2 --- CP Stacked Microstrip Patch Antenna Array --- p.92 / Chapter 6.3 --- Coplanar Waveguide-fed Slot Antenna --- p.93 / Chapter 6.4 --- Dual-band CP antenna fed by 2 different 90° hybrid couplers --- p.95 / Chapter Chapter 7 --- Novel New Dual-band CP Antenna Design --- p.96 / Chapter 7.1 --- Introduction --- p.96 / Chapter 7.2 --- Dual-band CP Patch Antenna --- p.96 / Chapter 7.2.1 --- Slotted Square Patch Antenna --- p.96 / Chapter 7.2.2 --- Slotted Cross Patch Antenna --- p.99 / Chapter 7.2.3 --- Simulation Results: Slotted Cross Patch Antenna --- p.101 / Chapter 7.3 --- Dual-band Quadrature Hybrid --- p.104 / Chapter 7.3.1 --- Simulation Results: Dual-band Hybrid Coupler --- p.107 / Chapter 7.4 --- Dual-band CP Antenna Realization --- p.113 / Chapter 7.4.1 --- Antenna Configuration --- p.113 / Chapter 7.4.2 --- Measurement Setup --- p.114 / Chapter 7.4.3 --- Experimental Results --- p.115 / Chapter Chapter 8 --- Conclusions and Recommendations for Future Work --- p.123 / Chapter 8.1 --- Filter --- p.123 / Chapter 8.2 --- Antenna --- p.123 / Chapter 8.3 --- Recommendations for future work --- p.124 / References --- p.125 / Author's Publications --- p.128 / Acronyms and Abbreviations --- p.129

The use of mobile bar code scanners is expanding to markets beyond popular manufacturing uses, such as healthcare, environmental testing and professional services. The successful interaction of users with mobile bar code scanners is of great importance from a business and technology perspective as well as from the user standpoint. Interaction problems associated with these devices may cause errors in data collection and affect job performance due to frustration, resulting in a potential impact on internal costs. The primary objective of this research was to develop design guidelines for the reengineering of keyboard designs for mobile bar code scanners. A secondary objective was to determine the effectiveness of current bar code scanner designs and how they can be related to other mobile technologies to develop a link across research areas. To accomplish these objectives, three different mobile bar code scanner keyboard designs were investigated: multiple-alphabetical, single-alphabetical and single split-Qwerty. A total of 42 subjects (18 females and 24 males) were recruited to participate in the experiment that was conducted to validate the research hypotheses. Time and accuracy data were recorded during the experiment and workload/subjective questionnaires were given to each participant following interaction with the different mobile bar code scanners. The following conclusions were reached based on the experimental results and are considered the major contributions of this research. First, an alphabetically laid out keyboard with multiple keys results in more time to find a character, a higher percentage of time spent typing incorrect lines, and a higher error rate than an alphabetically laid out keyboard with single keys. Perceived workload was also higher for a keyboard with multiple keys versus one with single keys. Second, no significant differences were found in the time to find a character, the percentage of time spent typing incorrect lines, and the error rate between keyboards with single keys, whether they are laid out alphabetically or in a split-Qwerty design. Finally, training a user on how to use a specific mobile bar code scanner keyboard layout often results in higher character rates, less time spent typing incorrect lines, and a lower error rate. / Graduation date: 2006