In measurement, the entire BBP design with the proposed gate-level structures exhibits high robustness in power supply and frequency variations. It can function normally at a minimum of 0.33 V power supply, which is over 100 mV below typical threshold voltage. In the test of the ACRL circuits, the ACRL cells show 30 - 70% delay reduction when compared to the standard static CMOS cells. And the ACRL custom PIE decoder works at the minimum of 0.26 V power supply, which is 40 mV lower than the minimum operating voltage archived by the PIE decoder in the BBP implemented with standard cells. / In this thesis, methodologies and examples are proposed for subthreshold digital circuit design. There is also a full study on subthreshold characteristics of devices and circuits in very-low-voltage operation. The EPC C1G2 baseband processor (BBP) for passive UHF (ultra high frequency) RFID (radio frequency identification) tag is selected as a subthreshold design example, as it is a digital design typified with instable very low supply voltage and requires ultra low power in operation. To tailor the BBP for lower operating voltage in subthreshold region, optimized structures and topologies are proposed in different hierarchical levels. In the system view, the BBP is partitioned according to the clock domain and the constraints of timing. Go down to the RTL and gate level, pipelining, parallelism, clock gating and one-hot state transition are implemented in the logic design according to the actual requirement. In this way energy awareness and power saving are achieved with enhanced robustness to operate in subthreshold region. The BBP with the proposed logic structures has been fabricated in several deep submicron CMOS technologies. Transistor level design is the bottom level for IC designers, the proposed active control ratioed logic (ACRL) is a logic style with fast pull-up network and less capacitance, particularly suitable for the implementation of high fan-in AOI-familiar (and-or-inverter) structure. Some general ACRL cells designs, 32-bit equality comparator and, a custom PIE decoder with ACRL cells, which is the important block of BBP with critical timing, have been fabricated in 130 nm CMOS technology. / Subthreshold designs are required in many actual applications. Especially, the subthreshold digital systems and circuits have become more and more popular in portable devices and passive systems. In conception subthreshold digital circuits are very-low-voltage circuits, they have great reduction of power consumption but suffer from long logic delay as the driving current for logic transition and propagation is greatly reduced. / Shi, Weiwei. / Adviser: C.S. Choy. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 146-152). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Finally, another new 0.5V fully differential wideband amplifier, which can be used in the wideband modulator, has been proposed. The gate-input two-stage amplifier employs a DC common-mode feedback circuit that uses a Miller-amplified capacitor for its frequency compensation. With the proposed technique, the power consumption of the low-voltage amplifier is drastically reduced. / Furthermore, a new dynamic CM level shifting technique for low-voltage CT delta-sigma modulators that employ a return-to-open feedback DAC is reported in the thesis. The technique maintains a stable CM level at the amplifier's inputs for this type of modulators. Simulation results show that it improves the modulator's SNDR by 11%. / In this thesis, we present research works on developing a low-voltage delta-sigma modulator with a wide signal bandwidth. Specifically, a 0.5V complex low-pass continuous-time (CT) third-order delta-sigma modulator that has a single-sided signal bandwidth of 1MHz, targeting for application in Bluetooth receivers, is presented without using any internal voltage boosting techniques which are potentially harmful to the reliability of the device. The wide bandwidth of the modulator at this low supply voltage is enabled by a special common-mode (CM) level arrangement in the system level and by new low-voltage amplifies. Realized in a 0.13mum CMOS process the proposed modulator achieves a 61.9-dB peak signal-to-noise-and-distortion ratio at the nominal supply of 0.5V with 3.4mW consumption, and occupies an active area of 0.9mm2. The modulator achieves the best figure-of-merit among its class. / The development of low-voltage design techniques for analog circuits has recently received a lot of attention due to the continuous shrinking of the supply voltage in modern CMOS technologies, which is projected to reduce to 0.5V for low power applications within ten years in the International Technology Roadmap for Semiconductor. This thesis focuses on developing circuit techniques for low-voltage delta-sigma modulator, a functional block that is widely used in mixed-signal integrated circuits. Several delta-sigma modulators operating at supply voltages below 0.9V have been reported in the open literature. However, none of them supports a signal bandwidth wider than 100kHz with a reasonable performance. / He, Xiaoyong. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2010. / Includes bibliographical references (leaves 104-111). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Tsang, Ka Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2009. / Includes bibliographical references. / Abstract also in Chinese. / Abstract / Acknowledgement / Content / Chapter 1. --- Introduction / Chapter 1.1 --- Motivation for Current-Mode Circuit --- p.1-1 / Chapter 1.2 --- Basic Current-Mode Building Block --- p.1-3 / Chapter 1.3 --- Adjoint Principle --- p.1-5 / Chapter 1.4 --- Characteristics of Current Amplifier --- p.1-8 / Chapter 1.5 --- Application of Current-Mode Circuit --- p.1-10 / Chapter 2. --- Conventional Design / Chapter 2.1 --- System Overview --- p.2-1 / Chapter 2.2 --- First Architecture and Circuit (Fully Current Mode) --- p.2-6 / Chapter 2.3 --- Second Architecture and Circuit (Voltage Mode) --- p.2-10 / Chapter 2.4 --- Performance Indicator --- p.2-15 / Chapter 3. --- Proposed Design / Chapter 3.1 --- Design Motivation --- p.3-1 / Chapter 3.2 --- Saturation Voltage Gain Stage (SVGS) --- p.3-7 / Chapter 3.3 --- Design 1: Current Amplifier with Boosted Saturation Voltage (Fully Current Mode) --- p.3-13 / Chapter 3.4 --- Design 2: Current Amplifier with Boosted Saturation Voltage (Voltage Mode) --- p.3-22 / Chapter 4. --- IC Measurement / Chapter 5. --- Conclusion / Chapter 5.1 --- Design 1: Current Amplifier with Boosted Saturation Voltage (Fully Current Mode) over Conventional Design --- p.5-1 / Chapter 5.2 --- Design 2: Current Amplifier with Boosted Saturation Voltage (Voltage Mode) over Conventional Design --- p.5-2 / Chapter 6. --- Future Idea / Chapter 7. --- Reference / Chapter 8. --- Appendix

Graduation date: 2005

The focus of this thesis involves development of highly transparent, n-channel, accumulation- mode thin-film transistors employing a zinc tin oxide (ZTO) channel layer. ZTO-based transparent thin-film transistors (TTFTs) show improved device performance compared to ZnO-based TTFTs. An estimated peak effective mobility for these devices as high as ~100 cm² V⁻¹sec⁻¹ has been observed, although effective mobilities in the range of 20-50 cm²V⁻¹sec⁻¹ are more common. This performance inconsistency may be due, in part, to the large device dimensions employed in developmental test structures and/or to shadow mask misalignment. Typical drain current on-to-off ratios are > 10⁶. Variation in the post-deposition annealing cycle is found to be an effective means to control the threshold voltage and to improve device performance. Optical characterization of these devices indicates ~84% transparency in the visible spectrum as viewed through the source/drain. Another aspect of this thesis research involves the utilization and extension of quantitative polycrystalline TFT device models with the intention of guiding the design and optimization of future TFTs. In particular, subthreshold conduction is assessed in order to estimate the bulk (and/or grain boundary) and interface trap densities. This leads to a consideration of threshold voltage and channel mobility extraction, as well as establishment of the turn-on voltage, V[subscript turn-on] Finally, a third aspect of this thesis research involves a new radio-frequency (RF) magnetron sputtering system, custom-designed and constructed at OSU by Chris Tasker. Contributions to the development of this tool include assisting in the design and implementation of the computer-controlled interlocks utilized for operation of the tool. The experimental flexibility of this new tool is discussed with respect to its applicability in the design and fabrication of future TTFTS. / Graduation date: 2004

In this thesis, a novel Direct-Charge-Transfer (DCT) integrator structure is proposed, which can settle much faster than regular switch-capacitor integrators. A new Spread-Spectrum Dynamic Element Matching (SS-DEM) algorithm is also introduced, which can effectively spread or shape the nonlinearity error of multi-bit DAC in the feedback path, thus improve the SNDR and THD performance of overall delta-sigma modulators. A three-bit quantizer design example is presented, which is embedded in a MASH2-0 structure delta-sigma modulator prototype and has been fabricated in AMI CMOS 1.5μm technology. Testing results indicate this quantizer works well. / Graduation date: 2004

Mass customization is promoted in manufacturing industry as a way to satisfy individual customer requirements in a flexible, efficient and cost effective way. However, mass customization within the specific sector of &lsquo / electronic consumer goods&rsquo / is relatively underdeveloped, whilst the contributions of industrial designers to mass customization remain quite unclear. This research redresses both of these issues, elaborating on the possibilities of mass-customization in the electronic consumer goods sector, and explaining how industrial designers can take a central role in implementation. Chapter 2 contains a literature review on key terms related to mass customization. A portfolio of mass customization case studies, from both within and outside electronic consumer goods, are presented and analyzed in Chapter 3, which also reports on a new classification system to define six discrete customization types. User needs research methods, including IDEO methods, are reviewed in Chapter 4 to determine those methods most applicable for use in the pilot (Chapter 5) and main (Chapter 7) &lsquo / research through design&rsquo / customization projects. The pilot project, conducted with METU industrial design undergraduates, explored opportunities and barriers for mass customization of electronic consumer goods / the main project, carried out by the Vestel ID Team under the SAN-TEZ scheme, resulted in a new mass customized all-in-one (AIO) PC for Vestel Electronics. In Chapter 6, results of interviews with Vestel staff are presented, uncovering the current situation within Vestel Electronics for implementing mass customization. Chapter 8 contains the research conclusions, including discussion of a proposed design-based mass customization design and development procedure.

Mass customization is promoted in manufacturing industry as a way to satisfy individual customer requirements in a flexible, efficient and cost effective way. However, mass customization within the specific sector of &lsquo / electronic consumer goods&rsquo / is relatively underdeveloped, whilst the contributions of industrial designers to mass customization remain quite unclear. This research redresses both of these issues, elaborating on the possibilities of mass-customization in the electronic consumer goods sector, and explaining how industrial designers can take a central role in implementation. Chapter 2 contains a literature review on key terms related to mass customization. A portfolio of mass customization case studies, from both within and outside electronic consumer goods, are presented and analyzed in Chapter 3, which also reports on a new classification system to define six discrete customization types. User needs research methods, including IDEO methods, are reviewed in Chapter 4 to determine those methods most applicable for use in the pilot (Chapter 5) and main (Chapter 7) &lsquo / research through design&rsquo / customization projects. The pilot project, conducted with METU industrial design undergraduates, explored opportunities and barriers for mass customization of electronic consumer goods / the main project, carried out by the Vestel ID Team under the SAN-TEZ scheme, resulted in a new mass customized all-in-one (AIO) PC for Vestel Electronics. In Chapter 6, results of interviews with Vestel staff are presented, uncovering the current situation within Vestel Electronics for implementing mass customization. Chapter 8 contains the research conclusions, including discussion of a proposed design-based mass customization design and development procedure.

This master thesis report contains information about a project carried out at Haldex Brake Products that is situated in Redditch England. The Redditch site is part of the “Commercial Vehicle Systems” division within the Haldex group. Haldex Brake Products is designing and producing electronic anti lock brake systems. The latest product is called GEN2 and the project goal was to increase productivity and achieve more stability within the production processes of this product. The goal was achieved trough implementation suggestions affecting the three categories in overall equipment efficiency (OEE). Nine of the biggest implementations are presented in this report. Some of the suggestions are already implemented and some are under progress to be implemented. These implementations will result in an increase in productivity with additionally 953 products per week. The expected results are based on calculations on an average product. The report also contains suggestions for future actions to even more increase the efficiency of the production processes at Haldex Brake Products in Redditch.

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