Delta-Sigma Modulator-based Analog-to-Digital converter design is an active area of research. New topologies require extensive simulations to verify their performance. A series of improvements were made to an existing circuit simulation package in order to speed the simulation process for the designer. Various examples of these improvements are presented in typical applications. / Graduation date: 1992

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As the technology scales, there is a need to develop design and optimization algorithms under various scenarios of uncertainties. These uncertainties are introduced by process variation and impact both delay and leakage. For future technologies at the end of CMOS scaling, not only process variation but the device defect density is projected to be very high. Thus realizing error tolerant implementation of Boolean functions with minimal redundancy overhead remains a challenging task. The dissertation is concerned with the challenges of low-power and area digital circuit design under high parametric variability and high defect density. The technology mapping provides an ideal starting point for leakage reduction because of higher structural freedom in the choices of implementations. We first describe an algorithm for technology mapping for yield enhancement that explicitly takes parameter variability into account. We then show how leakage can be reduced by accounting for its dependence on the signal state, and develop a fast gain-based technology mapping algorithm. In some scenarios the state probabilities can not be precise point values but are modeled as an interval. We extended the notion of mean leakage to the worst case mean leakage which is defined as the sum of maximal mean leakage of circuit gates over the feasible probability realizations. The gain-based algorithm has been generalized to optimize this proxy leakage metric by casting the problem within the framework of robust dynamic programming. The testing is performed by selecting various instance probabilities for the primary inputs that are deviations from the point probabilities with respect to which a point probability based gain based mapper has been run. We obtain leakage improvement for certain test probabilities with the interval probability based over the point probability based mapper. Next, we present techniques based on coding theory for implementing Boolean functions in highly defective fabrics that allow us to tolerate errors to a certain degree. The novelty of this work is that the structure of Boolean functions is exploited to minimize the redundancy overhead. Finally we have proposed an efficient analysis approach for statistical timing, which can correctly propagate the slope in the path-based statistical timing analysis. The proposed algorithm can be scaled up to one million paths.

Depuis quelques années, les explosifs artisanaux à base de peroxyde sont fréquemment utilisés dans les actes de terrorisme. Leur simplicité de conception ne les rend pas moins inoffensifs car ils sont tout aussi puissants que ceux à base de TNT (trinitrotoluène). Au regard des enjeux majeurs de la sécurité globale et en particulier de la protection du citoyen, il devient nécessaire de bénéficier d'instruments de détection fiables. C'est dans ce cadre que s'inscrit ce travail de thèse qui vise à développer un capteur intégré, sensible et sélectif aux traces d'explosifs, notamment ceux à base de peroxyde. Ce nez électronique est constitué d'une matrice de transistors à nanotubes de carbone (CNTFET) et d'une électronique et traitement des données. Après une brève introduction relative aux CNTFET pour la détection gazeuse, nous présentons les bases de l'élaboration d'une modélisation électrique du capteur. Cette modélisation a pour but, à terme, de permettre aux concepteurs decircuits intégrés de bénéficier d'un support de simulation des CNTFET, nécessaire à la mise en oeuvre de l'électronique de contrôle et de conditionnement des signaux. Nous détaillerons également ce qui constitue selon nous l'étape fondamentale précédant l'élaboration d'un modèle compact prédictif basé sur la physique, c'est à dire la compréhension topologique du réseau de nanotubes. Nous détaillerons alors différentes probabilités de contacts entre nanotubes. Nous présentons ensuite,l'élaboration de l'électronique permettant le contrôle des potentiels appliqués aux CNTFET et le conditionnement des signaux électriques. Ce conditionnement a pour objectif d'acheminer les réponses électriques du capteur vers des architectures de traitement de données utilisées pour la détection des différents gaz cibles. L'électronique intégrée en technologie CMOS HV (haute tension) est alimentée par pile basse tension. Des pompes de charge, élévateurs de tension, générant ces hautes tensions ont été étudiées, modélisées et réalisées. Nous proposons également dans ce manuscrit une nouvelle architecture de pompe de charge qui constitue, dans certaines plages d'utilisation, une alternative intéressante aux pompes de charge les plus performantes utilisées jusqu'à présent. / For the last few years, improvised peroxide based explosives are frequently used in acts of terrorism. Their simple design does not make them less threatening than those based on TNT because they are equally as powerful as those based on TNT (trinitrotoluene). In view of the major issues of the overall safety and, in particular, the citizens' protection, it becomes necessary to enjoy reliable detection instruments. Such is the background of this PhD work which aims to develop a built-in sensor,sensitive and selective to traces of explosives, especially those based on peroxide. This electronic nose is made up of a network of carbon nanotube field-effect transistors (CNTFET), and data processing hardware. After a brief introduction relating to CNTFETs for gaseous detection, we will provide the basis for the elaboration of an electronic modeling of the sensor. This modeling aims, at the end, to allow designers of integrated circuits to benefit from a simulation support of CNTFETs, required to the implementation of control and signal conditioning electronics. We will also detail what are the fundamental steps mandatory before the development of a predictive compact model based on physics, which means the topological understanding of the nanotubes network. Then, we will describe different probabilities of contacts between nanotubes. Later, we will introduce the elaboration of the electronics allowing the control of the voltages applied to the CNTFETs and the electrical signals conditioning. The objective of this conditioning is to carry electrical responses from the sensor to data processing architectures used for the detection of the different target gasses. High Voltage CMOS integrated electronics are powered by low-voltage batteries. Charge pumps and voltage boosters which generate these high voltages, have been investigated, modeled and carried out. We also provide in this dissertation a new charge pump architecture which offers, in some ranges of application, an interesting alternative to the most efficient charge pumps used until now.

Continuous-time (CT) Delta-Sigma Modulators (DSMs) have re-gained popularity recently for oversampling analog-to-digital conversion, because they are more suitable for low supply voltage implementation than their discrete-time (DT) counterparts, among other reasons. To the state of art at the low voltage front, a CT O.5-V audio-band DSM with a return-to-open feedback digital-to-analog converter has been reported. However, the O.5-V CT DSM has a limited performance of 74-dB SNDR due to clock jitters and other factors caused by the ultralow supply. / Finally, a O.5-V 2-1 cascaded CT DSM with SCR feedback is proposed. A new synthesis method is presented. Transistor-level simulations show that a 98dB SNDR is achieved over a 25-kHz signal bandwidth with a 6.4MHz sampling frequency and 350muW power consumption under a 0.5-V supply. / In this thesis, three novel ULV audio-band CT DSMs with high signal-to-noise-plus-distortion ratio (SNDR) are reported for a nominal supply of O.5V. The first one firstly realizes a switched-capacitor-resistor (SCR) feedback at O.5V, enabled by a fast amplifier at O.5V, for reduced clock jitter-sensitivity. Fabricated in a O.13mum CMOS process using only standard VT devices, the 3rd order modulator with distributed feedback occupies an active area of O.8mm2 . It achieves a measured SNDR of 81.2dB over a 25-kHz signal bandwidth while consuming 625muW at O.5-V. The measured modulator performance is consistent across a supply voltage range from O.5V to O.8V and a temperature range from -20°C to 90°C. Measurement results and thermal-noise calculation show that the peak SNDR is limited by thermal noise. / The scaling of the feature sizes of CMOS technologies results in a continuous reduction of supply voltage (VDD) to maintain reliability and to reduce the power dissipation per unit area for increasingly denser digital integrated circuits. The VDD for low-power digital circuits is predicted to drop to O.5V in about ten years. Ultra-low voltage (ULV) operation will also be required for the analog-to-digital converter, a universal functional block in mixed-signal integrated circuits, in situations where the benefits of using a single VDD out-weigh the overhead associated with multi-V DD solutions. / The second ULV CT DSM employs a feed-forward loop topology with SCR feedback. Designed in O.13mum CMOS process, the modulator achieves a post-layout simulation (thermal noise included) result of 89dB SNDR over a 25-kHz signal bandwidth. The 0.13mum CMOS chip consumes an active area of O.85mm2 and 682.5muW at O.5-V supply. It achieves an excellent measured performance of 87.8dB SNDR over a 25-kHz signal bandwidth and al02dB spurious-free dynamic range. To the best of our knowledge, this performance is the highest for DSMs in this supply voltage range. Thanks to the proposed adaptive biasing technique, the measured modulator performance is consistent across a supply voltage range from O.4V to O.75V and a temperature range from -20°C to 90°C. / Chen, Yan. / Adviser: Kong Pang Pun. / Source: Dissertation Abstracts International, Volume: 73-04, Section: B, page: . / Thesis (Ph.D.)--Chinese University of Hong Kong, 2011. / Includes bibliographical references (leaves 127-135). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstract also in Chinese.

Graduation date: 1996

Trends toward increased integration and miniaturization of optical system components have created pressure to consolidate widely disparate analog and digital functions onto fewer and fewer chips with a goal of eventually built into a single mixed-signal chip. Yet, because of those performance requirements, the frontend circuit has traditionally used III-V compound semiconductor technologies, but the low-level of integration with other digital ICs limits the sustainability of such end products for short-distance applications. On the other hand, their CMOS counter parts, despite having such advantages as low power consumption, high yield that lowers the cost of fabrication, and a higher degree of integration, have not performed well enough to survive in such a noisy environment without sacrificing other important attributes. In this research, a high-speed CMOS preamplifier was designed and fabricated through TSMC 0.18/spl mu/m mixed-signal non-epi CMOS technology, and a 20/spl mu/m diameter InGaAs thin-film Inverted-MSM photodetector with a responsivity of 0.15A/W at a wavelength of 1550/spl mu/m was post-integrated onto the circuit. The circuit has a overall transimpedance gain of 60dB/spl Omega/, and bit-error-rate data and eye-diagram measurement results taken as high as 10Gbit/s are reported in this dissertation.

This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized [alpha],[omega]-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N' --bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric/electrode surface treatment on the response of bottom-contact devices was also examined to maximize the device performance. Some of innovative techniques that employ the conducting polymer, poly(3,4-ethylenedioxythiophene) / poly(styrene sulfonate) (PEDOT/PSS) for the fabrication of OFETs, were compared and investigated. The device performance and the fabrication yield were also considered. Organic complementary ring oscillators and D flip-flops were demonstrated with PDI-8CN2 and pentacene as the n-type and ptype material, respectively. Both circuits recorded the highest speed that any organic transistor-based complementary circuit has achieved to date. The speed of these complementary circuits will be enhanced by increasing the mobility of n-channel further as well as reducing channel lengths and overlap capacitances between the source/drain electrodes and the gate. The semiconductors should be solution processible to be compatible with the inexpensive fabrication techniques envisioned for printed electronic circuits. PDI-8CN2 was used for solution-processed n-channel OFETs and the various parameters are compared for the optimization of devices. Utilizing optimized process parameters and surface treatments for solution-deposited PDI-8CN2 OFETs, we have successfully shown the first fabrication of complementary organic ring oscillators and Dflip flops by the micro-injection of the solution of both p-type and n-type materials in air. One of the potential platforms for low cost fabrication on flexible substrates is the use of inorganic semiconductor nanowires. Accordingly, the germanium nanowire FETs were fabricated and characterized. Conductivity enhanced PEDOT/PSS was employed as the electrode material for nanowire transistors to improve the electrical contacts to the source and drain. / text

The research investigates several critical design issues of continuous-time (CT) [Sigma Delta] modulators. The first is to investigate the sensitivity of CT [Sigma Delta] modulators to high-frequency clock spurs. These spurs down-convert the high-frequency quantization noise, degrading the dynamic range of the modulator. The second is to study the robustness of continuous-time loop filters under large RC product variations. Large RC variations in the CMOS process strongly degrade the performance of continuous-time [Sigma Delta] modulators, and reduce the production yield. The third is to model the harmonic distortion of one-bit continuous-time [Sigma Delta] modulators due to the interaction between the first integrator and the feedback digital-to-analog converter (DAC). A closed-form expression of the 3'rd-order harmonic distortion is derived and verified. Conventional CT [Sigma Delta] modulators employ all active integrators: each integrator needs an active amplifier. The research proposes a 5th-order continuous-time [Sigma Delta] modulator with a hybrid active-passive loop filter consisting of only three amplifiers. The passive integrators save power, and introduce no distortion. The active integrators provide gain and minimize internal noise contributions. A single-bit switched-capacitor DAC is employed as the main feedback DAC for high clock jitter immunity. An additional current steering DAC stabilizes the loop with the advantage of simplicity. To verify the proposed techniques, a prototype continuous-time [Sigma Delta] modulator with 2-MHz signal bandwidth is designed in a 0.25-¹m CMOS technology targeting for GPS or WCDMA applications. The experimental results show that the prototype modulator achieves 68-dB dynamic range over 2-MHz bandwidth with a 150-MHz clock, consuming 1.8 mA from a 1.5-V supply.

After World War II in the United States, the household refrigerator and freezer became interwoven into a domestic reality defined by consumption, mechanical innovation, and a tension between spatial isolation and cultural interconnectivity. This thesis positions narrative Hollywood cinema, television and print media as the dominant sites where the refrigerator and freezer’s social identities were formed and negotiated. These productions employ the devices to explore postwar family gender roles, the influence of culture industries and consumer economies within the home, and technological fantasies and fears. They also illustrate a fertile conversation between household media technologies and kitchen accessories. As a result, viewing the refrigerator and freezer through film and television representations substantially alters existing conclusions over who interacted with the objects on an everyday basis, and their effect for a culture increasingly reliant upon appliances to provide basic human needs and generate a satisfying, entertaining lifestyle. / text