An in-circuit emulator (ICE) is an important tool for the development of microprocessor-based systems. External ICE boxes are complex and expensive piece of hardware so their use is usually limited to debugging phases of the microprocessor-based systems that involve hardware/software integration or investigation of real time I/O or bus events. On the other hand, a ROM monitor is inexpensive, but provides less observablity for the microprocessor¡¦s operations. In either case, the design practice of the ICE devices is usually independent to the design task of the microprocessor itself. The performance and cost of the ICE devices are not relevant to the microprocessors since they are two different entities. The ICE¡¦s are used only during the development/debugging of the microprocessor-based systems by substituting the original microprocessor on the socket with the ICE. The ICE is unplugged after debugging and the original microprocessor is placed back into the socket for normal operations of the microprocessor-based systems. Therefore, the performance and cost of the ICE¡¦s do not impact these of the microprocessor-based systems because the ICE¡¦s do not exist in them. We then define three feasible solutions software, hardware and hybrid) and integrate them with a synthesizable ARM7 icroprocessor core. The microprocessors with the embedded ICE¡¦s are synthesized and simulated to analyze and compare the corresponding hardware/software performance and cost and the debugging features of these approaches.

With the advanced of the technique, we can design more IP in the same area space chip. The embedded system has more powerful about its application. We need to have a more efficient core processor to support the whole embedded system in complex system environment. The main purpose of this paper is increased the calculated speed, memory management and debugging for SYS32TME III, which is designed by our lab as an ARM10 like processor. We integrate the cache/MMU and EICE( Embedded in-circuit emulator ) into the embedded processor core. Using the cache/MMU, we can not only speed up the processor which access external memory time but also use the virtual address for Operating System. In order to keep the correctness of the system and speed up the system integration time, we use five functional (cache off, cache on and MMU off with cache hit/miss, cache on and MMU on with cach hit/cache miss and TLB hit/cache miss and TLB miss) tests to verify the cache/MMU and six coprocessor instructions (LDC, MCR, MCRR, MRC, MRRC, STC ) to verify the EICE. After that, we also use the regression test about the microprocessor, cache/MMU and EICE system integration. In the end, we turned the performance about the integrated cache/MMU and EICE, so that we can support an 200MHz ARM 10-like processor by 0.18£gm.

Embedded in circuit emulator (EICE) is the most common and widely used debugging techniques for microprocessors. Because the ICE is capable to provide diverse debugging and testing mechanisms, such as: single-step debugging, breakpoints setting and detection, monitoring, and modification of internal resources. However, the shortcoming of the conventional embedded in circuit emulator (EICE) is that the operation of the processor has to be suspended during debugging, which is categorized as static debugging (Static Debug) and is infeasible for real-time debugging. Therefore, this paper proposes a design alternative to support the real-time system debugging without suspending the microprocessor via the debug hardware Coprocessor14 (the Debug Coprocessor). In this paper, the embedded in circuit emulator is combined with Coprocessor 14 to provide both the static debugging and Run-time system debugging. After incorporating CP14 with the debugging mechanism, the control of the debug hardware is no longer limited to use the IEEE 1149.1 test port during debugging. On the other hand, the set of debugging constraints and the observation of the internal state of the microprocessor can be achieved by inserting the Coprocessor instruction at the program level.