Recently, various special purpose processors have been developed and are frequently being used for different specialized tasks. Prominent among these are the communication processors, which are generally used within an embedded system environment. Such processors can run relatively advanced and general purpose operating systems such as uCLinux, which is a freely available embedded Linux distribution. In this work, a prototype SoHo (Small office / Home office) router is designed and implemented using Motorola MCF5272 as the core communication processor and uCLinux as the operating system. The implementation relies purely on the existing hardware resources of an available development board and the publicly available open source utilities of uCLinux. The overall development process provides an embedded system implementation and configuration example.

The objective of this study is to implement a low-cost smart camera application on a Commercial off the Shelf system that is based on Texas Instrument&rsquo / s DM3730 System on Chip processor. Although there are different architectures for smart camera applications, ARM plus DSP based System on Chip architecture is selected for implementation because of its different core abilities. Beagleboard-XM platform that has an ARM plus DSP based System on Chip processor is chosen as Commercial off the Shelf platform. During this thesis, firstly to start-up the Commercial off the Shelf platform the design steps of porting an embedded Linux to ARM core of System on Chip processor is described. Then design steps that are necessary for implementation of smart camera applications on both ARM and DSP cores in parallel are given in detail. Furthermore, the real-time image processing performance of the Beagleboard-xM platform for the smart camera applications is evaluated with simple implementations.

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Frequency dynamics is one of the most important signals of a power system, and it is an indicator of imbalance between generation and load in the system. The Internet-based real-time GPS-synchronized wide-area Frequency Monitoring Network (FNET) was proposed to provide imperative frequency dynamics information for a variety of system-wide monitoring, analysis and control applications. The implementation of FNET has for the first time made the synchronized observation of the entire U.S. power network possible with very little cost. The FNET is comprised of many Frequency Disturbance Recorders (FDR) geographically dispersed throughout the U.S. and an Information Management System (IMS), currently located at Virginia Tech. The FDR works as a sensor, which performs local measurements and transmits calculations of frequency, voltage magnitude and voltage angle to the remote servers via the Internet. Compared with its commercial counterpart Phasor Measurement Unit (PMU), FDR provides less expensive version for networked high-resolution real-time synchronized. The improved single phase algorithm in the FDRs made it possible to measure at 110V level which is much more challenging than PMUs due to the noise involved at this level. This research work presents the challenges and issues of both software and hardware design for the novel measurement device FDR, which is one of the devices with the highest dynamic precision for power system frequency measurement. The DFT-based Phasor Angle Analysis algorithm has been improved to make sure the high-resolution measuring FDRs are installed at residential voltage outlets, instead of substation high-voltage inputs. An embedded 12-channel timing GPS receiver has been integrated to provide an accurate timing synchronization signal, UTC time stamp, and unit location. This research work also addresses the harmonics, voltage swing and other noise components' impacts on the measurement results, and the optimized design of filters and a coherent sampling scheme to reduce or eliminate those impacts. The verification test results show that the frequency measurement accuracy of the FDR is within +/-0.0005Hz, and the time synchronization error is within +/-500ns with suitable GPS antenna installation. The preliminary research results show the measurement accuracy and real-time performance of the FDR are satisfactory for a variety of FNET applications, such as disturbance identification and event location triangulation. / Ph. D.

The Master Thesis deals with the design of hardware component interconnection inference algorithm that is supposed to be used in the FPGA schema editor that was integrated into educational integrated development environment VLAM IDE. The aim of the algorithm is to support user by finding an optimal interconnection of two given components. The editor and the development environment are implemented as an Eclipse plugin using GMF framework. A brief description of this technologies and the embedded systems design are followed by the design of the inference algorithm. This problem is a topic of combinatorial optimization, related to the bipartite matching and assignment problem. After this, the implementation of the algorithm is described, followed by tests and a summary of achieved results.