This thesis describes the implementation of zero-cost auto-tuning techniques for embedded Proportional Integral and Derivative (PID) controllers, specifically focusing on their application in the control of proportional valves within Micro Gas Chromatography (uGC) systems. uGC systems are miniaturized versions of conventional GC systems, and require precise temperature, flow and pressure control for the micro-fabricated preconcentrators and micro columns. PID controllers are widely used in process control applications due to their simplicity and effectiveness. The Commercial Off The Shelf (COTS) available controllers are expensive, bulky, need system compatibility and have high lead times. The proposed auto-tuner features simple Python-implemented empirical calculations based on Ziegler Nichols relay-based PID tuning method to determine the optimal PID gains. Leveraging Wi-Fi the system enables tuning for any embedded platform while visualizing transient response through the Graphical User Interface (GUI). The embedded-GUI interface provides a customizable auto-tuning experience extending usage across diverse temperature, pressure and flow regulation applications in environmental analysis. Specifically for uGC systems, the GUI integrates with existing hardware stack using minor software enhancements to enable rapid, automated PID tuning for thermal and flow control applications. The performance is analyzed by evaluating response metrics including overshoot, rise time, and steady-state error. / Master of Science / Commercially available flow and thermal regulators are expensive and bulky. In applications like micro gas chromatography (uGC) systems, these commercial tools to regulate actuator control reduce portability and may require different regulators for different control ranges. To overcome these challenges, we developed an open-source, transparent Proportional-Integral-Derivative (PID) auto-tuner for micro-electromechanical systems (MEMS) actuators in uGC systems. The proposed Python-based Graphical User Interface (GUI) approach leverages simple empirically-driven calculations to determine optimal gains. By interfacing with any embedded system through standard connection like Wi-Fi, the auto-tuner enables interactive, vendor-agnostic tuning while visualizing full transient response. This provides accessible, customizable auto-tuning capabilities to enhance closed-loop PID control across instrumentation and device applications at no or minimal additional hardware cost. In uGC systems, we utilize the same setup for thermal, flow, and pressure control, with additional sensor costs offset by the implementation of multiple closed loops on the same system.Precise temperature and flow control is critical in many applications, such as minimizing fluctuations in analyte retention times in uGC systems. PID control offers reliable closed-loop control for such applications, but tedious manual tuning is required for each system. The proposed auto-tuner presented in this work will greatly simplify PID tuning to improve temperature and flow rate precision in these systems. The performance is analyzed by evaluating response metrics including overshoot, rise time, and steady-state error. This thesis discusses the auto-tuning technique, PID implementation, and experimental performance analysis. Overall, this work presents a novel embedded PID automated methodology for rapid and precise thermal and flow control in uGC and other precision regulation applications. The proposed auto-tuning method provides effective tuning across a wide variety of applications such as motors, temperature and pressure control, and flow regulation systems.

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Design of real-time embedded systems is a complex and challenging task. Part of this complexity originates from their limited resources which incurs handling a big range of Non-Functional Requirements (NFRs). Therefore, satisfaction of NFRs plays an important role in the correctness of the design of these systems. Model-driven development has the potential to reduce the design complexity of real-time embedded systems by increasing the abstraction level, enabling analysis at earlier phases of development and code generation. In this thesis, we identify some of the challenges that exist in model-driven development of real-time embedded systems with respect to NFRs, and provide techniques and solutions that aim to help with the satisfaction of NFRs. Our end goal is to ensure that the set of NFRs defined for a system is not violated at runtime. First, we identify and highlight the challenges of modeling NFRs in telecommunication systems and discuss the application of a UML-based approach for modeling them. Since NFRs have dependencies, and the design decisions to satisfy them cannot be considered in isolation, we propose a model-based approach for trade-off analysis of NFRs to help with the comparison of different design models with respect to the satisfaction level of their NFRs. Following the issue of evaluating the interdependencies of NFRs, we also propose solutions for establishing and maintaining balance between different NFRs. In this regard, we categorize our suggested solutions into static and dynamic. The former refers to a static design and set of features which ensures and guarantees the balance of NFRs, while the latter means establishing balance at runtime by reconfiguring the system and runtime adaptation. Finally, we discuss the role of the execution platform in preservation and monitoring of timing properties in real-time embedded systems and propose an approach to enrich the platform with necessary mechanisms for monitoring them. / CHESS

Quality assurance of dependable embedded systems is becoming increasingly difficult, as developers are required to build more complex systems on tighter budgets. As systems become more complex, system architects must make increasingly complex architecture design decisions. The process of making the architecture design decisions of an intended system is the very first, and the most significant, step of ensuring that the developed system will meet its requirements, including requirements on its ability to tolerate faults. Since the decisions play a key role in the design of a dependable embedded system, they have a comprehensive effect on the development process and the largest impact on the developed system. Any faulty architecture design decision will, consequently, propagate throughout the development process, and is likely to lead to a system not meeting the requirements, an unacceptable level of dependability and costly corrections. Architecture design decisions are in turn critical with respect to quality and dependability of a system, and the cost of the development process. It is therefore crucial to prevent faulty architecture design decisions and, as early as practicable, detect and remove faulty decisions that have not successfully been prevented. The use of Architecture Description Languages (ADLs) helps developers to cope with the increasing complexity by formal and standardized means of communication and understanding. Furthermore, the availability of a formal description enables automated and formal analysis of the architecture design. The contribution of this licentiate thesis is an architecture quality assurance framework for safety-critical, performance-critical and mission-critical embedded systems specified by the Architecture Analysis and Design Language (AADL). The framework is developed through the adaption of formal methods, in particular traditional model checking and model-based testing techniques, to AADL, by defining formal verification criteria for AADL, and a formal AADL-semantics. Model checking of AADL models provides evidence of the completeness, consistency and correctness of the model, and allows for automated avoidance of faulty architecture design decisions, costly corrections and threats to quality and dependability. In addition, the framework can automatically generate test suites from AADL models to test a developed system with respect to the architecture design decisions. A successful test suite execution provides evidence that the architecture design has been implemented correctly. Methods for selective regression verification are included in the framework to cost-efficiently re-verify a modified architecture design, such as after a correction of a faulty design decision. / Kvalitetssäkring av tillförlitliga inbyggda system är en ständigt växande utmaning då utvecklare av sådana system är tvungna att bygga allt mer komplexa system inom allt mer begränsade budgetar. Då komplexiteten av systemen ökar måste systemarkitekter göra allt mera komplicerade beslut om systemens arkitekturdesign. Processen att besluta arkitekturdesignen av ett tilltänkt system är det allra första, och det mest signifikanta, steget att försäkra att det utvecklade systemet kommer uppnå dess krav, inklusive krav på dess möjlighet att tolerera defekter. Då dessa designbeslut dessutom har en nyckelroll i designen av ett tillförlitligt inbyggt system har de en omfattande effekt på utvecklingsprocessen samt den största påverkan på det utvecklade systemet. På grund av detta kommer ett felaktigt beslut om arkitekturdesignen propagera igenom hela utvecklingsprocessen och sannolikt resultera i ett system som inte uppnår kraven, får en oacceptabel tillförlitlighetsnivå, och kostsamma korrigeringar. De är därmed kritiska med hänsyn till kvaliteten och tillförlitligheten av ett inbyggt system, och kostnaden av utvecklingsprocessen. Således är det kritiskt att förhindra felaktiga beslut om arkitekturdesign och, så tidigt som möjligt, detektera och avlägsna felaktiga beslut som inte har lyckats att förhindras. Användningen av språk för arkitekturbeskrivning hjälper utvecklare att hantera den ökande komplexiteten genom standardiserade kommunikationsmedel och förståelsemedel. Dessutom möjliggör en formell beskrivning automatiserad och formell analys av arkitekturdesignen. Bidraget av denna licentiatavhandling är ett formellt kvalitetssäkringsramverk för säkerhetskritiska, prestandakritiska och uppdragskritiska inbyggda system specificerade i arkitekturbeskrivningsspråket ”Architecture Analysis and Design Language” (AADL). Ramverket är utvecklat genom adaptionen av formella metoder, i synnerhet traditionella modellkontrolltekniker och modellbaserad testningstekniker, till AADL, med hjälp av att definiera formella verifikationskriterier för AADL och en formell AADL-semantik. Modellkontroll av AADL-modeller analyserar modellens fullständighet, konsistens och korrekthet och möjliggör automatisk undvikande av felaktiga arkitekturdesignbeslut, kostsamma korrigeringar och hot mot kvalitet och tillförlitlighet. Därutöver kan ramverket automatiskt generera testsviter från AADL-modeller för att testa ett utvecklat system mot den bestämda arkitekturdesignen. En lyckad testsvitexekvering garanterar att arkitekturdesignen är korrekt implementerad. Metoder för selektiv regressionsverifiering är inkluderade i ramverket för att på ett kostnadseffektivt tillvägagångssätt verifiera en, tidigare verifierad, arkitekturdesign som har blivit modifierad, såsom efter en korrigering av ett felaktigt designbeslut.

Currently, there is lack of effective and scalable methods to specify and ana-lyze requirements specifications, and verify the behavioral models of embed-ded systems. Most embedded systems requirements are expressed in naturallanguage which is flexible and intuitive but frequently ambiguous, vague andincomprehensive. Besides to natural language, template-based requirementsspecification methods are used to specify requirements specifications (esp. insafety-critical applications), which reduce ambiguity and improves the com-prehensibility of the specifications. However, the template-based method areusually rigid due to the fixed structures of the templates. They also lack meta-models for extensibility, and template selection is challenging.In this thesis, we proposed a domain specific language for embedded sys-tems, called ReSA, which is constrained natural language but flexible enoughto allow engineers to use different constructs to specify requirements. Thelanguage has formal semantics in proportional logic and description logic thatenables non-trivial and rigorous analysis of requirements specification, e.g.,consistency checking, completeness of specifications, etc.Moreover, we propose a scalable formal verification of Simulink models,whichisusedtodescribethebehaviorofsystemsthroughcommunicatingfunc-tional blocks. In industry, Simulink is the de facto modeling and analysis en-vironment of embedded systems. It is also used to generate code automati-cally from special Simulink models for various hardware platforms. However,Simulink lacks formal approach to verify large and hybrid Simulink models.Therefore, we also propose a formal verification of Simulink models, repre-sented as stochastic timed automata, using statistical model checking, whichhas proven to scale for industrial applications.We validate our approaches on industrial use cases from the automotiveindustry. These includes Adjustable Speed Limiter (ASL) and Brake-By-Wire(BBW) systems from Volvo Group Trucks Technology, both safety-critical. / Verispec

There exists an increasing demand for computing power and performance in real-time embedded systems, as new, more complex customer requirements and function-alities are appearing every day. In order to support these requirements and func-tionalities without breaking the power consumption wall, many embedded systems areswitching from traditional single-core hardware architectures to multi-core architec-tures. Multi-core architectures allow for parallel execution of tasks on the multiplecores. This introduces many benets from the perspective of achievable performance,but in turn introduces major issues when it comes to the timing predictability ofthe real-time embedded system applications deployed on them. The problem arisesfrom unpredictable and potentially unbounded inter-core interferences, which occuras a result of contention for the shared resources, such as the shared system busor shared system memory. This thesis studies the possible application of constraintprogramming as a resource optimization technique for the purpose of creating oineschedules for tasks in real-time embedded system applications executing on a dual-core architecture. The main focus is placed on tightening inter-core data-propagationinterferences, which can result in lower over-all data-propagation delays. A proto-type of an optimization engine, employing constraint programming techniques on ap-plications comprised of tasks structured according to the Phased Execution Model isdeveloped. The prototype is evaluated through several experiments on a large numberof industry inspired intellectual-property free benchmarks. Alongside the experimentsa case study is conducted on an example engine-control application and the resultingschedule is compared to a schedule generated by the Rubus-ICE industrial tool suite.The obtained results show that the proposed method is applicable to a potentially widerange of abstract systems with dierent requirements. The limitations of the methodare also discussed and potential future work is debated based on these results. / <p>Presentation was held over Zoom, due to the COVID-19 situation.</p>

Networks connected to the internet are under a constant threat of attacks. To protect against such threats, new techniques utilising already connected hardware have in this thesis been proven to be a viable solution. By equipping network switches with lightweight machine learning models, such as, Decision Tree and Random Forest, no additional devices are needed to be installed on the network.When an attack is detected, the device may notify or take direct actions on the network to protect vulnerable systems. By utilising container software on Westermo's devices, a model has been integrated, limiting its computational resources. Such a system, and its building blocks, are what this thesis has researched and implemented. The system has been validated using multiple different models using a range of parameters.These models have been trained offline on datasets with pre-recorded attacks. The recordings are converted into flows, decreasing dataset size and increasing information density. These flows contain features corresponding to information about the packets and statistics about the flows. During training, a subset of features was selected using a Genetic Algorithm, decreasing the time for processing each packet. After the models have been trained, they are converted to C code, which runs on a network switch. These models are verified online, using a simulated factory, launching different attacks on the network. Results show that the hardware is sufficient for smaller models and that the system is capable of detecting certain types of attacks.

There are scenarios in the modern world of today when several things are being cooked at the same time on the stove in the kitchen. You typically have a saucepan that is boiling a carbohydrate. This requires attention and can result in elevated levels of mental exertion. Would it not be useful then to aid the cooking process by removing the boiling process as a point of attention by automating the boiling process?   Food to be boiled can be identified through image recognition. There is thus a possibility to automate boiling by using machine learning. In this project machine learning is used to automate the boiling of carbohydrates. A prototype has been developed which consists of a camera and a Raspberry Pi in which a convolutional neural network (CNN) model has been implemented. The prototype can identify pasta, potato, rice, their corresponding boiling states, and give correct indication when any of them is ready. A dataset has been created from scratch, containing 5607 images that were taken and labeled, and then used to train the CNN model.   The CNN model has been evaluated through a confusion matrix applied to an image dataset which was captured by the prototype. It was also evaluated through tables of successful boiling trials. The evaluation results show that the performance of the CNN model can identify carbohydrates in limited stove scenarios. The confusion matrix shows that the precision scores are 0.846, 0.959, 0.870, 0.688 for pasta, potato, rice and "no boiling item", respectively. Recall scores are 0.967, 0.848, 0.844 and 0.681 for pasta, potato, rice and "no boiling item", respectively. But it is not sufficiently reliable to be able to work in a wide range of scenarios because of the limited dataset. It has also been shown that it is possible to use the CNN model to guide the boiling of carbohydrates. But still the dataset is not sufficiently large to quantify the error rate of the boiling system. There is potential for this type of application but further work is needed.

<p dir="ltr">Dynamic analysis of embedded firmware is a necessary capability for many security tasks, e.g., vulnerability detection. Rehosting is a technique that enables dynamic analysis by facilitating the execution of firmware in a host environment decoupled from the actual hardware. Current rehosting techniques focus on high-fidelity execution of the entire firmware. Consequently, these techniques try to execute firmware in an emulated environment, with precise models of hardware (i.e., peripheral) interactions. However, these techniques are hard to scale and have various drawbacks. </p><p dir="ltr">Therefore, a novel take on rehosting is proposed by focusing on the application components and their interactions with the firmware without the need to model hardware dependencies. This is achieved by rehosting the embedded application as a Linux application. In addition to avoiding precise peripheral modeling, such a rehosting technique enables the use of existing dynamic analysis techniques on these embedded applications. The feasibility of this approach is demonstrated first by manually performing the rehosting on real-world embedded applications. The challenges in each of the phases – retargeting to x86-64, peripheral handling, and fuzzing the rehosted applications are elaborated. Furthermore, automated steps for retargeting to the x86-64 and peripheral handling are developed. The peripheral handling achieves 89% accuracy if reserved regions are also considered. The testing of these rehosted applications found 2 previously unknown defects in driver components.</p>

To catch up with the growing trend of parallelism, this thesis work focuses on the adaption of embedded real-time systems to a multicore platform. We use the embedded system of Xilinx ZCU-102, a multicore board, as an example of an embedded system without getting deep into its architecture. First, we deal with the tasks required to be able to make an embedded system operational and discuss why they are different from those for normal computer systems. The processes it takes to make a custom operating system for the given Xilinx embedded system are examined and patching the custom operating system along with customizing it is studied. We then take a look at related work in the field of benchmarking real-time systems and embedded systems and with a good understanding of related work propose a design similar to the related work for benchmarking embedded systems. The benchmarks we use run on multiple cores and aim at challenging the Xilinx board’s capabilities of running real-time tasks when the other cores on the board are occupied with performing independent tasks. We test the designed benchmarks on different conditions under two different operating systems of RT-Linux and Embedded Linux to study the differences between them. We then note how the RT-Linux would be a real upgrade for real-time systems if multicore operations are considered. The final result we have obtained is that core idling might decrease the performance of real-time tasks and RT-Linux might experience more interrupts but it is also better at recovering from interrupts.