Es wurde das Lebendnierenspendeprogramm der Universitätsklinik Würzburg anhand der statistischen Auswertung von 40 Transplantationen im Zeitraum von 1992-2003 untersucht. Dabei werden prä-, intra- und postoperative Verläufe von Spendern und Empfängern beschrieben sowie mit Ergebnissen anderer Transplantationszentren verglichen. Die Ergebnisse sind hierbei als zufriedenstellend zu bezeichnen.

Die vorliegende Arbeit befasst sich mit dem Entwurf eines monolithisch integrierten 60-GHz-Empfängerschaltkreises in einer modernen Silizium-Germanium-Halbleitertechnologie mit 190 GHz maximaler Transitfrequenz. Drei für die Entwicklung von MMIC-Empfängerschaltkreisen äußerst wichtige Prinzipien liegen dem Entwurf zugrunde: die Optimierung von Rauschverhalten und Bandbreite sowie die Betrachtung der maximal erreichbaren Ausgangsleistung. Diese Prinzipien werden detailliert untersucht und typische Schaltungen dahingehend analysiert. Insbesondere wird eine Methode vorgestellt, die es erlaubt, die maximale Ausgangsleistung für die häufig verwendete Kaskodestufe vorherzusagen. Dabei handelt es sich um eine Erweiterung der Methode der Lastkurve nach Cripps. Weiterhin werden Ansätze zur Modellierung von Leitungen vorgestellt und ihre Verwendbarkeit für die unterschiedlichen Simulationsarten diskutiert. Der Hauptteil der Arbeit behandelt den Entwurf des Empfängerschaltkreises, welcher aus einem breitbandigen Eingangsverstärker mit niedrigem Rauschen und einstellbarer Verstärkung, einem Leistungsteiler, einem direkten Quadratur-Abwärtsmischer, einem Basisbandverstärker, einem Treiberverstärker für das Lokaloszillatorsignal sowie einem 90°-Phasenschieber besteht. Zusätzlich sind verschiedene Referenzstrom- und -spannungsquellen im Schaltkreis integriert. Die gefertigte Schaltung wurde messtechnisch vollständig charakterisiert, und alle Ergebnisse sind wiedergegeben. Der gemessene Mischgewinn beträgt bis zu 40 dB bei einer Bandbreite von mehr als 15 GHz. Die Zweiseitenbandrauschzahl liegt bei moderaten 7,5 dB. Die gemessene Phasen- und Amplitudenabweichung sind geringer als 5° und geringer als 0,15 dB. Die Gesamtschaltung nimmt 360 mW Leistung aus einer 2,2-V-Spannungsquelle auf. Insbesondere die Bandbreite des Empfängerschaltkreises stellt eine Verbesserung des aktuellen Standes der Technik dar. / The present work studies the development of a monolithic 60 GHz receiver IC in a modern 190 GHz-fT silicon-germanium semiconductor technology. The design is based on three fundamental principles, which are of great importance for MMIC receiver design: noise optimisation, bandwidth enhancement and output power considerations. Those principles are discussed in detail, and typical circuit examples are comprehensively analysed. Specifically, a method is presented that allows the prediction of output power for the frequently-used cascode stage. This method is an extension of Cripps’ load line theory. Furthermore, modelling approaches for transmission lines and their suitability for various types of simulations are discussed. The main part focuses on the design process of the receiver IC, which consists of a broadband low noise amplifier with variable gain, a power divider, a zero-IF quadrature mixer, a baseband amplifier, an LO driver amplifier and a 90°-phase shifter. Additionally, several reference current and voltage sources are implemented in the IC. The manufactured circuit is characterised in detail, and all measurement results are presented. Over a bandwidth of more than 15 GHz, the measured conversion gain is up to 40 dB with a moderate double sideband noise figure of 7.5 dB. An I/Q imbalance measurement reveals a phase accuracy of better than 5° and an amplitude error of less than 0.15 dB. The total power consumption is 360 mW from a 2.2 V-source. Particularly in terms of bandwidth, the circuit performance exceeds the current state of the art.

Die vorliegende Arbeit befasst sich mit dem Entwurf eines monolithisch integrierten 60-GHz-Empfängerschaltkreises in einer modernen Silizium-Germanium-Halbleitertechnologie mit 190 GHz maximaler Transitfrequenz. Drei für die Entwicklung von MMIC-Empfängerschaltkreisen äußerst wichtige Prinzipien liegen dem Entwurf zugrunde: die Optimierung von Rauschverhalten und Bandbreite sowie die Betrachtung der maximal erreichbaren Ausgangsleistung. Diese Prinzipien werden detailliert untersucht und typische Schaltungen dahingehend analysiert. Insbesondere wird eine Methode vorgestellt, die es erlaubt, die maximale Ausgangsleistung für die häufig verwendete Kaskodestufe vorherzusagen. Dabei handelt es sich um eine Erweiterung der Methode der Lastkurve nach Cripps. Weiterhin werden Ansätze zur Modellierung von Leitungen vorgestellt und ihre Verwendbarkeit für die unterschiedlichen Simulationsarten diskutiert. Der Hauptteil der Arbeit behandelt den Entwurf des Empfängerschaltkreises, welcher aus einem breitbandigen Eingangsverstärker mit niedrigem Rauschen und einstellbarer Verstärkung, einem Leistungsteiler, einem direkten Quadratur-Abwärtsmischer, einem Basisbandverstärker, einem Treiberverstärker für das Lokaloszillatorsignal sowie einem 90°-Phasenschieber besteht. Zusätzlich sind verschiedene Referenzstrom- und -spannungsquellen im Schaltkreis integriert. Die gefertigte Schaltung wurde messtechnisch vollständig charakterisiert, und alle Ergebnisse sind wiedergegeben. Der gemessene Mischgewinn beträgt bis zu 40 dB bei einer Bandbreite von mehr als 15 GHz. Die Zweiseitenbandrauschzahl liegt bei moderaten 7,5 dB. Die gemessene Phasen- und Amplitudenabweichung sind geringer als 5° und geringer als 0,15 dB. Die Gesamtschaltung nimmt 360 mW Leistung aus einer 2,2-V-Spannungsquelle auf. Insbesondere die Bandbreite des Empfängerschaltkreises stellt eine Verbesserung des aktuellen Standes der Technik dar. / The present work studies the development of a monolithic 60 GHz receiver IC in a modern 190 GHz-fT silicon-germanium semiconductor technology. The design is based on three fundamental principles, which are of great importance for MMIC receiver design: noise optimisation, bandwidth enhancement and output power considerations. Those principles are discussed in detail, and typical circuit examples are comprehensively analysed. Specifically, a method is presented that allows the prediction of output power for the frequently-used cascode stage. This method is an extension of Cripps’ load line theory. Furthermore, modelling approaches for transmission lines and their suitability for various types of simulations are discussed. The main part focuses on the design process of the receiver IC, which consists of a broadband low noise amplifier with variable gain, a power divider, a zero-IF quadrature mixer, a baseband amplifier, an LO driver amplifier and a 90°-phase shifter. Additionally, several reference current and voltage sources are implemented in the IC. The manufactured circuit is characterised in detail, and all measurement results are presented. Over a bandwidth of more than 15 GHz, the measured conversion gain is up to 40 dB with a moderate double sideband noise figure of 7.5 dB. An I/Q imbalance measurement reveals a phase accuracy of better than 5° and an amplitude error of less than 0.15 dB. The total power consumption is 360 mW from a 2.2 V-source. Particularly in terms of bandwidth, the circuit performance exceeds the current state of the art.

Since its invention, cellular communication has dramatically transformed personal lifes and the evolution of mobile networks is still ongoing. Evergrowing demand for higher data rates has driven development of 3G and 4G systems, but foreseen 5G requirements also address diverse characteristics such as low latency or massive connectivity. It is speculated that the 4G plain cyclic prefix (CP)-orthogonal frequency division multiplexing (OFDM) cannot sufficiently fulfill all requirements and hence alternative waveforms have been in-vestigated, where generalized frequency division multiplexing (GFDM) is one popular option. An important aspect for any modern wireless communication system is the application of multi-antenna, i.e. MIMO techiques, as MIMO can deliver gains in terms of capacity, reliability and connectivity. Due to its channel-independent orthogonality, CP-OFDM straightforwardly supports broadband MIMO techniques, as the resulting inter-antenna interference (IAI) can readily be resolved. In this regard, CP-OFDM is unique among multicarrier waveforms. Other waveforms suffer from additional inter-carrier interference (ICI), inter-symbol interference (ISI) or both. This possibly 3-dimensional interference renders an optimal MIMO detection much more complex. In this thesis, weinvestigate how GFDM can support an efficient multiple-input multiple-output (MIMO) operation given its 3-dimensional interference structure. To this end, we first connect the mathematical theory of time-frequency analysis (TFA) with multicarrier waveforms in general, leading to theoretical insights into GFDM. Second, we show that the detection problem can be seen as a detection problem on a large, banded linear model under Gaussian noise. Basing on this observation, we propose methods for applying both space-time code (STC) and spatial multiplexing techniques to GFDM. Subsequently, we propose methods to decode the transmitted signals and numerically and theoretically analyze their performance in terms of complexiy and achieved frame error rate (FER). After showing that GFDM modulation and linear demodulation is a direct application of Gabor expansion and transform, we apply results from TFA to explain singularities of the modulation matrix and derive low-complexity expressions for receiver filters. We derive two linear detection algorithms for STC encoded GFDM signals and we show that their performance is equal to OFDM. In the case of spatial multiplexing, we derive both non-iterative and iterative detection algorithms which base on successive interference cancellation (SIC) and minimum mean squared error (MMSE)-parallel interference cancellation (PIC) detection, respectively. By analyzing the error propagation of the SIC algorithm, we explain its significantly inferior performance compared to OFDM. Using feedback information from the channel decoder, we can eventually show that near-optimal GFDM detection can outperform an optimal OFDM detector by up to 3dB for high SNR regions. We conclude that GFDM, given the obtained results, is not a general-purpose replacement for CP-OFDM, due to higher complexity and varying performance. Instead, we can propose GFDM for scenarios with strong frequency-selectivity and stringent spectral and FER requirements.

With the recent advancements of wireless networks to satisfy new requirements, the investigation of novel transmission schemes to improve the link level performance is of major importance. A very common technique utilized in nowadays systems is the Orthogonal frequency division multiplexing (OFDM) waveform, which has been adopted by several standards, including WiFi, LTE, and more recently 5G, due to its simple equalization process. Despite its success, this dissertation shows that OFDM is a sub-optimal scheme under frequency-selective channel (FSC), when channel state information (CSI) is available at the receiver only. Based on the coded modulation capacity approach, this work demonstrates that the data symbols should experience the same channel gain in order to achieve the best performance, leading to the equal gain criterion (EGC). However, this comes at a cost in terms of losing orthogonality among data symbols. The result is valid for linear modulation matrices under the assumptions of CSI at only at the receiver with perfect feedback equalization. In order to attain the EGC for doubly-dispersive channels, the block multiplexing (BM) waveform is proposed in this thesis, where the data symbols are spread in frequency and time. For instance, the recently conceived orthogonal time frequency space (OTFS) is shown to be a particular case of BM with the classical single-carrier (SC). Regarding the equalization for the robust waveforms, it is shown that the minimum mean squared error with parallel interference cancellation (MMSE-PIC) employed together with convolutional encoder and soft decoder can completely remove the inter-symbol interference (ISI), where a low-complexity implementation is designed. In addition, a waveform with decreased complexity based on the sparse Walsh-Hadamard (SWH) is proposed for two reasons, i) sparse spreading requires a transform with lower size, ii) the Walsh-Hadamard transform is implemented with 1s and −1s, which requires less complexity than fast Fourier transform (FFT) based waveforms. Furthermore, the problem of estimating the time varying channel is considered, where a unique word (UW) or (pilot block) based approach is studied. In this regard, another main contribution of this dissertation is to develop an optimization framework, where the combination of channel estimation plus Doppler spread error is minimized. In particular, the composite error minimization is achieved by properly setting the FFT size of the system, for a fixed data length. Lastly, cyclic prefix (CP)-free system is considered such that the transmission time is decreased, and therefore provides a better channel estimation. Naturally, the CP-free system has undesirable interference, which is resolved by an iterative CP-Restoration algorithm. In this case, we extend the EGC to equal reliability criterion (ERC), i.e., the data symbols should be equally reliable and not only have equal gain. As a consequence, the BM with orthogonal chirp division multiplexing (OCDM) waveform has the best performance due to equal time and frequency spreading. In conclusion, the coded modulation capacity approach of this dissertation provides new insights and solutions to improve the performance of wireless systems.

The Internet of Things (IoT) is leading the world to the Internet of Everything (IoE), where things, people, intelligent machines, data and processes will be connected together. The key to enter the era of the IoE lies in enormous sensor nodes being deployed in the massively expanding wireless sensor networks (WSNs). By the year of 2025, more than 42 billion IoT devices will be connected to the Internet. While the future IoE will bring priceless advantages for the life of mankind, one challenge limiting the nowadays IoT from further development is the ongoing power demand with the dramatically growing number of the wireless sensor nodes. To address the power consumption issue, this dissertation is motivated to investigate low-power wake-up receivers (WuRXs) which will significantly enhance the sustainability of the WSNs and the environmental awareness of the IoT. Two proof-of-concept low-power WuRXs with focuses on two different application scenarios have been proposed. The first WuRX, implemented in a cost-effective 180-nm CMOS semiconductor technology, operates at 401−406-MHz band. It is a good candidate for application scenarios, where both a high sensitivity and an ultra-low power consumption are in demand. Concrete use cases are, for instance, medical implantable applications or long-range communications in rural areas. This WuRX does not rely on a further assisting semiconductor technology, such as MEMS which is widely used in state-of-the-art WuRXs operating at similar frequencies. Thus, this WuRX is a promising solution to low-power low-cost IoT. The second WuRX, implemented in a 45-nm RFSOI CMOS technology, was researched for short-range communication applications, where high-density conventional IoT devices should be installed. By investigation of the WuRX for operation at higher frequency band from 5.5 GHz to 7.5 GHz, the nowadays ever more over-traffic issues that arise at low frequency bands such as 2.4 GHz can be substantially addressed. A systematic, analytical research route has been carried out in realization of the proposed WuRXs. The thesis begins with a thorough study of state-of-the-art WuRX architectures. By examining pros and cons of these architectures, two novel architectures are proposed for the WuRXs in accordance with their specific use cases. Thereon, key WuRX parameters are systematically analyzed and optimized; the performance of relevant circuits is modeled and simulated extensively. The knowledge gained through these investigations builds up a solid theoretical basis for the ongoing WuRX designs. Thereafter, the two WuRXs have been analytically researched, developed and optimized to achieve their highest performance. Proof-of-concept circuits for both the WuRXs have been fabricated and comprehensively characterized under laboratory conditions. Finally, measurement results have verified the feasibility of the design concept and the feasibility of both the WuRXs.

Interest in millimeter (mm-) wave frequencies covering the spectrum of 30-300 GHz has been steadily increasing. Advantages such as larger absolute bandwidth and smaller form-factor have made this frequency region attractive for numerous applications, including high-speed wireless communication, sensing, material science, health, automotive radar, and space exploration. Continuous development of silicon-germanium heterojunction bipolar transistor (SiGe HBT) and associated BiCMOS technology has achieved transistors with fT/fmax of 505/720 GHz and integration with 55 nm CMOS. Such accomplishment and predictions of beyond THz performance have made SiGe BiCMOS technology the most competitive candidate for addressing the aforementioned applications. Especially for mobile applications, a critical demand for future mm-wave applications will be low DC power consumption (Pdc), which requires a substantial reduction of supply voltage and current. Conventionally, reducing the supply voltage will lead to HBTs operating close to or in the saturation region, which is typically avoided in mm-wave circuits due to expectated performance degradation and often inaccurate models. However, due to only moderate speed reduction at the forward-biased base-collector voltage (VBC) up to 0.5 V and the accuracy of the compact model HICUM/L2 also in saturation, low-power mm-wave circuits with SiGe HBTs operating in saturation offer intriguing benefits, which have been explored in this thesis based on 130 nm SiGe BiCMOS technologies: • Different low-power mm-wave circuit blocks are discussed in detail, including low-noise amplifiers (LNAs), down-conversion mixers, and various frequency multipliers covering a wide frequency range from V-band (50-75 GHz) to G-band (140-220 GHz). • Aiming at realizing a better trade-off between Pdc and RF performance, a drastic decrease in supply voltage is realized with forward-biased VBC, forcing transistors of the circuits to operate in saturation. • Discussions contain the theoretical analysis of the key figure of merits (FoMs), topology and bias selection, device sizing, and performance enhancement techniques. • A 173-207 GHz low-power amplifier with 23 dB gain and 3.2 mW Pdc, and a 72-108 GHz low-power tunable amplifier with 10-23 dB gain and 4-21 mW Pdc were designed. • A 97 GHz low-power down-conversion mixer was presented with 9.6 dB conversion gain (CG) and 12 mW Pdc. • For multipliers, a 56-66 GHz low-power frequency quadrupler with -3.6 dB peak CG and 12 mW Pdc, and a 172-201 GHz low-power frequency tripler with -4 dB peak CG and 10.5 mW Pdc were realized. By cascading these two circuits, also a 176-193 GHz low-power ×12 multiplier was designed, achieving -11 dBm output power with only 26 mW Pdc. • An integrated 190 GHz low-power receiver was designed as one receiving channel of a G-band frequency extender specifically for a VNA-based measurement system. Another goal of this receiver is to explore the lowest possible Pdc while keeping its highly competitive RF performance for general applications requiring a wide LO tuning range. Apart from the low-power design method of circuit blocks, the careful analysis and distribution of the receiver FoMs are also applied for further reduction of the overall Pdc. Along this line, this receiver achieved a peak CG of 49 dB with a 14 dB tunning range, consuming only 29 mW static Pdc for the core part and 171 mW overall Pdc, including the LO chain. • All designs presented in this thesis were fabricated and characterized on-wafer. Thanks to the accurate compact model HICUM/L2, first-pass access was achieved for all circuits, and simulation results show excellent agreement with measurements. • Compared with recently published work, most of the designs in this thesis show extremely low Pdc with highly competitive key FoMs regarding gain, bandwidth, and noise figure. • The observed excellent measurement-simulation agreement enables the sensitivity analysis of each design for obtaining a deeper insight into the impact of transistor-related physical effects on critical circuit performance parameters. Such studies provide meaningful feedback for process improvement and modeling development.:Table of Contents Kurzfassung . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1 Introduction 1 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of symbols and acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Technology 7 2.1 Fabrication Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 SiGe HBT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 B11HFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 SG13G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 SG13D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Commonly Used Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Grounded-sidewall-shielded microstrip line . . . . . . . . . . . . . . . . . . 12 2.2.2 Zero-impedance Transmission Line . . . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.3.1 Active Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3.2 Passive Balun . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Low-power Low-noise Amplifiers 25 3.1 173-207 GHz Ultra-low-power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.1 Topology Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.2 Bias Dependency of the Small-signal Performance . . . . . . . . . . . . . 27 3.1.2.1 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.1.2.2 Bias vs Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.1.2.3 Bias vs Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.1.2.4 Bias vs Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.1.3 Bias selection and Device sizing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.1 Bias Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.3.2 Device Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.1.4 Performance Enhancement Technologies . . . . . . . . . . . . . . . . . . . 41 3.1.4.1 Gm-boosting Inductors . . . . . . . . . . . . . . . . . . . . . . . 41 3.1.4.2 Stability Enhancement . . . . . . . . . . . . . . . . . . . . . . . 43 3.1.4.3 Noise Improvement . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.1.5 Circuit Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.1 Layout Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.1.5.2 Inductors Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1.5.3 Dual-band Matching Network . . . . . . . . . . . . . . . . . . . 48 3.1.5.4 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.6 Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.6.3 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2 72-108 GHz Low-Power Tunable Amplifier . . . . . . . . . . . . . . . . . . . . . . 55 3.2.1 Configuration, Sizing, and Bias Tuning Range . . . . . . . . . . . . . . . . 55 3.2.2 Regional Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.1 Impedance Variation . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.2.2 Regional Matching Network Design . . . . . . . . . . . . . . . . 60 3.2.3 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.2.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4 Low-power Down-conversion Mixers 73 4.1 97 GHz Low-power Down-conversion Mixer . . . . . . . . . . . . . . . . . . . . . 74 4.1.1 Mixer Design and Implementation . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.1 Mixer Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.1.1.2 Bias Selection and Device Sizing . . . . . . . . . . . . . . . . . . 77 4.1.1.3 Mixer Implementation . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5 Low-power Multipliers 87 5.1 General Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.2 56-66 GHz Low-power Frequency Quadrupler . . . . . . . . . . . . . . . . . . . . 89 5.3 172-201 GHz Low-power Frequency Tripler . . . . . . . . . . . . . . . . . . . . . 93 5.4 176-193 GHz Low-power ×12 Frequency Multiplier . . . . . . . . . . . . . . . . . 96 5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6 Low-power Receivers 101 6.1 Receiver Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.2 LO Chain (×12) Integrated 190 GHz Low-Power Receiver . . . . . . . . . . . . . 104 6.2.1 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.2 Low-power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.3 Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.1 LNA and LO DA . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.3.2 Tunable Mixer and IF BA . . . . . . . . . . . . . . . . . . . . . 111 6.2.3.3 65 GHz (V-band) Quadrupler . . . . . . . . . . . . . . . . . . . 116 6.2.3.4 G-band Tripler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.4 Receiver Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . 123 6.2.5 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.2.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7 Conclusions 133 7.1 Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7.2 Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Bibliography 135 List of Figures 149 List of Tables 157 A Derivation of the Gm 159 A.1 Gm of standard cascode stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 A.2 Gm of cascode stage with Lcas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 A.3 Gm of cascode stage with Lb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 B Derivation of Yin in the stability analysis 163 C Derivation of Zin and Zout 165 C.1 Zin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 C.2 Zout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 D Derivation of the cascaded oP1dB 169 E Table of element values for the designed circuits 171

This work investigates a 5.5–7.5-GHz band-configurable duty-cycled wake-up receiver (WuRX) fully implemented in a 45-nm radio-frequency (RF) silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) technology. Based on an uncertain intermediate frequency (IF) super-heterodyne receiver (RX) topology, the WuRX analogue front-end (AFE) incorporates a 5.5–7.5-GHz band-tunable low-power low-noise amplifier, a low-power Gilbert mixer, a digitally controlled oscillator (DCO), a 100-MHz IF band-pass filter (BPF), an envelope detector, a comparator, a pulse generator and a current reference. By application of duty cycling with a low duty cycle below 1%, the power consumption of the AFE was significantly reduced. In addition, the on-chip digital bank-end consists of a frequency divider, a phase corrector, a 31-bit correlator and a serial peripheral interface. A proof-of-concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45-nm RF-SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. Tested at 8 operation bands covering 5.5–7.7 GHz, the WuRX has a measured sensitivity between −67.5 dBm and −72.4 dBm at a wake-up error rate of 10−3. With the sensitivity unchanged, the data rate of the WuRX can be scaled up to 8.2 kbps. To the authors' best knowledge, this work offers the largest RF bandwidth from 5.5 to 7.5 GHz, the most operation channels (≥8) and the fastest settling time (<115 ns) among the WuRXs reported to date.

For ultra-high speed communication systems at high center frequencies above 100 GHz, we propose a disruptive change in system architecture to address major issues regarding amplifier chains with a large number of amplifier stages. They cause a high noise figure and high power consumption when operating close to the frequency limits of the underlying semiconductor technologies. Instead of scaling a classic homodyne transceiver system, we employ repeated amplification in single-stage amplifiers through positive feedback as well as synthesizer-free self-mixing demodulation at the receiver to simplify the system architecture notably. Since the amplitude and phase information for the emerging oscillation is defined by the input signal and the oscillator is only turned on for a very short time, it can be left unstabilized and thus come without a PLL. As soon as gain is no longer the most prominent issue, relaxed requirements for all the other major components allow reconsidering their implementation concepts to achieve further improvements compared to classic systems. This paper provides the first comprehensive overview of all major design aspects that need to be addressed upon realizing a SPARS-based transceiver. At system level, we show how to achieve high data rates and a noise performance comparable to classic systems, backed by scaled demonstrator experiments. Regarding the transmitter, design considerations for efficient quadrature modulation are discussed. For the frontend components that replace PA and LNA amplifier chains, implementation techniques for regenerative sampling circuits based on super-regenerative oscillators are presented. Finally, an analog-to-digital converter with outstanding performance and complete interfaces both to the analog baseband as well as to the digital side completes the set of building blocks for efficient ultra-high speed communication.

In ultra-low power Wireless Sensor Networks (WSNs) sensor nodes need to interact, depending on the application, even at a rapid pace while preserving battery life. Wireless communication brings thereby quite the burden as the radio transceiver requires a relative huge amount of power during both transmission or reception phases. In WSNs with on demand communication, the sensor nodes are required to maintain responsiveness and to act the sooner they receive a request, reducing the overall latency of the network. The aspect is more challenging in asynchronous WSN as the receiver possesses no information about the packet arrival time. In a purely on-demand communication, duty-cycling shows little to almost no improvement. The receiving node, in such scheme, is expected to last for years while also being accessible to other peers. Here arises the utility of an external ultra-low power radio receiver known as Wake-up Receiver (WuRx). Its essential task is to remain as the only part of the system running while the rest of the systems enters the lowest power mode (i.e., sleep state). Once a request signal is received, it notifies the host processor and other peripherals for an incoming communication. With the sensor node being in sleep state (WuRx active only), substantial power levels can be achieved. If the WuRx is able to interact rapidly, the added latency remains negligible. As crucial performance figures, the sensitivity and bit rate are immediately affected by the extreme low-power budget at diifferent magnitudes, depending mainly on the incorporated architecture. This thesis focuses on the design of a feature-balanced WuRx. The passive radio frequency architecture (PRF) relies on passive detection while consuming zero power to extract On-Off-Keying (OOK) modulated envelopes. The featured sensitivity, however, is reduced compared to more complex architectures. A WuRx based on PRF architecture can effectively enable short-range applications. The sensitivity can vary with respect to several parameters including the total generated noise, circuit technology and topology. Two variants of the PRF WuRxs are introduced with the baseband amplifier being the main change. The first revision employs a high performance amplifier with reduced average energy consumption, thanks to a novel power gating control. The second variant focuses on employing an ultra-low power baseband amplifier as it is expected to be in a continuous active state. This thesis also brings the necessary analysis on the passive front-end with the intention to enhance the overall WuRx sensitivity. Proof of concepts are embedded in sensor node boards and feature -61 dBm and -64 dBm of sensitivity for the first and the second variant, respectively, at a packet-error-rate (PER) of 1% whilst demanding a similar power of 7.2 µW during packet listening. During packet decoding, the first variant demands a 150 µW of power, caused greatly by the baseband amplifier. The achieved latency is less than 30 ms and the bit rate is 4 kbit/s, Manchester encoding. For long-range applications, a higher sensitivityWuRx is proposed based on Tuned-RF (TRF) architecture. By embedding a low-noise amplifier (LNA) in the receiver chain, very weak radio signal can be detected. TheWuRx emphasizes higher sensitivity of -90 dBm. The design of the LNA prioritized the highest gain and lowest bias current by sacrifcing the linearity that poses little impact on signal integrity for the OOK modulated signals. The total active power consumption of the TRF WuRx is 1.38 mW. In this work, a fast sampling approach based on power gating protocol allows a drastic reduction in energy consumption on average. By being able to sample in matter of few microseconds, the WuRx is able to detect the presence of a packet and return to sleep state right after packet decoding. Being power-gated dropped the average power consumption to 2.8 µW at a packet detection latency of 32 ms for less than 2 s of interval time between communication requests. The proposed solutions are able to decode a minimum length of 16-bit pattern and operate in the license-free ISM band 868 MHz. This thesis also includes the analysis and implementation of low-power front-end building blocks that are employed by the proposed WuRx.:1 Introduction 1.1 Motivation 1.2 Wake-up Receiver Design Requirements 1.2.1 Energy Consumption 1.2.2 Network Coverage and Robustness 1.2.3 Wake-up Packet Addressing 1.2.4 WuPt Detection Latency 1.2.5 Hosting System, Form-factor and Fabrication Technology 1.3 Thesis Organisation 2 Wireless Sensor Networks 2.1 Radio Communication 2.1.1 Electromagnetic Spectrum 2.1.2 Link Budget Analysis 2.2 Asynchronous Radio Receiver Duty-cycle Control 2.2.1 B-MAC and X-MAC Protocols 2.2.2 Energy and Latency Analysis 2.3 Power Supply Requirements 2.3.1 Low Self-discharge Battery 2.3.2 Energy Harvester 2.4 Summary 3 State-of-the-Art of Wake-up Receivers 3.1 Wake-up Receiver Architectural Analysis 3.1.1 Passive RF Detector 3.1.2 Classical Radio Architectures 3.2 Wake-up Receiver Back-end Stages 3.2.1 Baseband Amplifiers 3.2.2 Analog to Digital Conversion 3.2.3 Wake-up Packet Decoder 3.3 Power Consumption Reduction at Circuit Level 3.3.1 Power Gating 3.3.2 Interference Rejection and Filtering 3.4 Summary 4 Proposal of Novel Wake-up Receivers 4.1 Ultra-low Power On-demand Communication in Wireless Sensor Networks: Challenges and Requirements 4.2 Passive RF Wake-up Receiver 4.3 Power-gated Tuned-RF Wake-up Receiver 5 Low-power RF Front-end 5.1 Narrow-band Low-noise Amplifier (LNA) 5.1.1 Topology 5.1.2 Voltage Gain 5.1.3 Stability 5.1.4 Noise Figure 5.1.5 Linearity 5.2 Envelope Detector 5.2.1 Theory of Square-law Detection and Sensitivity Analysis 5.2.2 Single-Diode Envelope Detector 5.2.3 Voltage Multiplier Envelope Detector 5.3 Hardware Assessment 5.3.1 LNA 5.3.2 Envelope Detector 5.4 Summary 6 Passive RF Wake-up Receiver 6.1 Circuit Implementation 6.1.1 Address Decoder 6.1.2 Envelope Detector 6.1.3 Power-gated Baseband Amplifier 6.1.4 Ultra Low-power Baseband Amplifier 6.2 Experimental Results 6.2.1 Wireless Sensor Node 6.2.2 Measurements 6.3 Summary 7 Power-gated Tuned-RF Wake-up Receiver 7.1 Power-gating Protocol 7.2 Circuit Design 7.2.1 Radio Front-end 7.2.2 Data Slicer 7.2.3 Digital Baseband 7.3 Performance Evaluation 7.4 Summary 8 Conclusion 8.1 Performance Summary 8.2 Future Perspective 8.3 Applications A Two-tone Simulation Setup B Diode Models and Simulation Setup C Preamble Detection C Code Implementation Bibliography Publications / In drahtlosen Sensornetzwerken (WSNs) mit extrem geringem Stromverbrauch müssen Sensorknoten je nach Anwendung kurze Latenzzeiten erreichen ohne die Batterielebensdauer zu beeinträchtigen. Die drahtlose Kommunikation bringt dabei eine ziemliche Belastung mit sich, da der Funktransceiver sowohl während der Sende- als auch der Empfangsphase relativ viel Strom benötigt. Einige marktfähige Funktransceiver benötigen durchschnittlich ca. 10 mA im Empfangsmodus sowie 30 mA im Sendemodus. Deshalb wird heutzutage das sogenannte Duty-Cycling mit bestimmten Sende-, Empfangs- und langen Schlafzeitintervallen eingeführt. Während der Schlafphase ist der Empfänger nicht ansprechbar. Was wiederum zu einer massiven Erhöhung der Latenzzeit führen kann. In vielen Anwendungen und insbesondere im Rahmen der Digitalisierung von Prozessen wird mittlerweile die Fähigkeit On-Demand mit sehr kurzen Latenzzeiten zu kommunizieren verlangt. Diese Anforderung steht in einem Wiederspruch zum genannten Duty-cycle Betrieb. Um dieses Dilemma zu lösen wird im Rahmen dieser Doktorarbeit ein Funkempfänger mit extrem geringen Stromverbrauch untersucht und entwickelt. Mit Hilfe des extrem niedrigen Stromverbrauches kann der Funkempfänger ständig empfangsbereit sein. Er wird zum Hauptempfänger mit dem hohen Stromverbrauch zugeschaltet, so dass nur nach Aufforderung der Hauptempfänger aktiv sein wird. Dieser Empfänger wird Wake-up Empfänger (WuRx) genannt. Seine wesentliche Aufgabe besteht darin, als einziger Teil des Gesamtknotens aktiv zu sein, während der Rest in den Modus mit dem niedrigsten Stromverbrauch versetzt wird. Sobald ein Anforderungssignal empfangen wird, weckt er den Haupt-Prozessor und andere Peripheriegeräte über eine eingehende Kommunikation. Somit ist der Aufweckempfänger essenziell für die Zuverlässigkeit der drahtlosen Kommunikation. Sein Stromverbrauch sollte im µA Bereich sein. Seine Empfangsbereitschaft hängt entscheidend von seiner Empfindlichkeit sowie Bitrate ab. Eine Verbesserung der Empfindlichkeit und Erhöhung der Bitrate würden zwangsläufig zu einer Erhöhung des Stromverbrauches führen. Im Rahmen dieser Doktorarbeit werden unterschiedliche Architekturen von Aufweckempfängern untersucht und umgesetzt. Zusammenhänge zwischen Empfindlichkeit, Bitrate und Stromverbrauch wurden analysiert und mögliche Grenzen gezeigt. Ein wesentliches Augenmerk war dabei, Off-the-Shelf Komponenten zu verwenden. Im Rahmen dieser Doktorabeit wurden in Abhängigkeit von der zu erreichenden Reichweite und Häufigkeit der Kommunikation zwei wesentliche Architekturen mit geeigneten Empfindlichkeiten und extrem geringem Stromverbrauch entwickelt. Für kurze Reichweiten wurde eine passive Hochfrequenzarchitektur (PRF Architektur) basierend auf einer passiven Erkennung von OOK-modulierten (On-Off-Keying) Signalen mittels Hüllkurvenbildung entwickelt. Die erreichte Empfindlichkeit von ca. -64 dBm stellt eine wesentliche Verbesserung gegenüber dem Stand der Technik und Forschung mit einer Empfindlichkeit von ca. -52 dBm dar. Die Empfindlichkeit kann in Bezug auf verschiedene Parameter variieren, einschließlich des insgesamt erzeugten Rauschens, der Schaltungstechnologie und der Topologie. Zwei Varianten der PRF WuRxs wurden realisiert, wobei der Basisbandverstärker die Hauptänderung darstellt. Die erste Version verwendet einen Hochleistungsverstärker mit reduziertem durchschnittlichen Energieverbrauch dank einer neuartigen Leistungssteuerung. Die zweite Variante konzentriert sich auf die Verwendung eines Basisbandverstärkers mit extrem geringer Leistung, da erwartet wird, dass er sich in einem kontinuierlichen aktiven Zustand befindet. Diese Arbeit bringt auch die notwendige Analyse des passiven Front-Ends mit der Absicht, die allgemeine WuRx-Empfindlichkeit zu verbessern. Nachweise der Wirksamkeit sind in Sensorknotenmodulen eingebettet und verfügen über -61 dBm und -64 dBm Empfindlichkeit für die erste bzw. die zweite Variante bei einer Paketfehlerrate (PER) von 1 %, während beim Abhören von Paketen eine ähnliche Leistung von 7.2 µW gefordert wird. Während der Paketdecodierung erfordert die erste Variante eine Leistung von 150 µW, die stark durch den Basisbandverstärker verursacht wird. Die erreichte Latenz beträgt weniger als 30 ms und die Bitrate beträgt 4 kbit/s mit einer Manchester-Codierung. Für Anwendungen mit großer Reichweite wird ein WuRx mit höherer Empfindlichkeit vorgeschlagen. Dieser basiert auf einer TunedRF (TRF) -Architektur. Dabei werden sehr schwache Funksignale durch einen rauscharmen Verstärker (LNA) erkannt und verstärkt. Der WuRx erreicht eine bessere Empfindlichkeit von ca. –90 dBm. Dabei wurde das Augenmerk auf die höchste Verstärkung verbunden mit dem niedrigsten Vorspannungsstrom gelegt. Der LNA wird dann im nicht-linearen Bereich betrieben. Dieser Betriebsmodus beeinflusst nur im geringeren Maße die Signalintegrität der OOK-modulierten Signale. Der gesamte Leistungsverbrauch des TRF WuRx beträgt 1.38 mW. Um den Gesamtleistungsverbrauch im µW Bereich zu reduzieren, wird im Rahmen dieser Arbeit das sogenannte Power-Gating-Protokoll eingeführt. Dabei wird das Funkkanal zyklisch abgetastet. Der WuRx kann innerhalb von wenigen Mikrosekunden das Vorhandensein eines Pakets erkennen und direkt nach der Paketdecodierung in den Ruhezustand zurückkehren. Durch diesen Ansatz konnte der durchschnittliche Stromverbrauch bei einer Paketerkennungslatenz von ca. 32 ms innerhalb einer Abtastrate von 2 s auf 2.8 µW reduziert werden. Die vorgeschlagenen Lösungen können eine Mindestlänge von 16-Bit-Mustern decodieren und im lizenzfreien ISM-Band 868 MHz arbeiten.:1 Introduction 1.1 Motivation 1.2 Wake-up Receiver Design Requirements 1.2.1 Energy Consumption 1.2.2 Network Coverage and Robustness 1.2.3 Wake-up Packet Addressing 1.2.4 WuPt Detection Latency 1.2.5 Hosting System, Form-factor and Fabrication Technology 1.3 Thesis Organisation 2 Wireless Sensor Networks 2.1 Radio Communication 2.1.1 Electromagnetic Spectrum 2.1.2 Link Budget Analysis 2.2 Asynchronous Radio Receiver Duty-cycle Control 2.2.1 B-MAC and X-MAC Protocols 2.2.2 Energy and Latency Analysis 2.3 Power Supply Requirements 2.3.1 Low Self-discharge Battery 2.3.2 Energy Harvester 2.4 Summary 3 State-of-the-Art of Wake-up Receivers 3.1 Wake-up Receiver Architectural Analysis 3.1.1 Passive RF Detector 3.1.2 Classical Radio Architectures 3.2 Wake-up Receiver Back-end Stages 3.2.1 Baseband Amplifiers 3.2.2 Analog to Digital Conversion 3.2.3 Wake-up Packet Decoder 3.3 Power Consumption Reduction at Circuit Level 3.3.1 Power Gating 3.3.2 Interference Rejection and Filtering 3.4 Summary 4 Proposal of Novel Wake-up Receivers 4.1 Ultra-low Power On-demand Communication in Wireless Sensor Networks: Challenges and Requirements 4.2 Passive RF Wake-up Receiver 4.3 Power-gated Tuned-RF Wake-up Receiver 5 Low-power RF Front-end 5.1 Narrow-band Low-noise Amplifier (LNA) 5.1.1 Topology 5.1.2 Voltage Gain 5.1.3 Stability 5.1.4 Noise Figure 5.1.5 Linearity 5.2 Envelope Detector 5.2.1 Theory of Square-law Detection and Sensitivity Analysis 5.2.2 Single-Diode Envelope Detector 5.2.3 Voltage Multiplier Envelope Detector 5.3 Hardware Assessment 5.3.1 LNA 5.3.2 Envelope Detector 5.4 Summary 6 Passive RF Wake-up Receiver 6.1 Circuit Implementation 6.1.1 Address Decoder 6.1.2 Envelope Detector 6.1.3 Power-gated Baseband Amplifier 6.1.4 Ultra Low-power Baseband Amplifier 6.2 Experimental Results 6.2.1 Wireless Sensor Node 6.2.2 Measurements 6.3 Summary 7 Power-gated Tuned-RF Wake-up Receiver 7.1 Power-gating Protocol 7.2 Circuit Design 7.2.1 Radio Front-end 7.2.2 Data Slicer 7.2.3 Digital Baseband 7.3 Performance Evaluation 7.4 Summary 8 Conclusion 8.1 Performance Summary 8.2 Future Perspective 8.3 Applications A Two-tone Simulation Setup B Diode Models and Simulation Setup C Preamble Detection C Code Implementation Bibliography Publications