The time-domain finite difference (TD-FD) method is applied to obtain the frequency-dependent characteristics of shielded multiconductor microstrip line interconnect structures. A Gaussian pulse is used as the excitation source and the reflected, transmitted, and coupled pulses on the various lines are used for the calculation of the frequency-dependent elements in the scattering matrix representation of the structure. In order to correctly specify the frequency range of applicability of the results, the cutoff frequencies of the higher-order modes of the structures under consideration need to be found. This is done by a two-dimensional application of the TD-FD method over the cross-section of the multiconductor transmission line, based on the simple observation that modes at cutoff are characterized by the fact that ∂/∂z = 0 where z is the direction of propagation along the axis of the line. Numerical results are obtained for the dispersive characteristics of coupled microstrip lines and the frequency-dependent scattering parameters of a microstrip open-end line, a 90° bend, a right-angle via, and the discontinuity which occurs when one of the two lines is terminated in a coupled symmetric microstrip geometry.

A constant frequency diode-clamped series resonant power converter (CFCSRC) is proposed as a solution to problems associated with frequency-controlled resonant converters. This converter has two resonant frequencies, and control is achieved by varying the relative time per switching cycle spent at each resonant frequency. Two zero-current-switching (ZCS) modes are examined and plotted in the output plane. Operating and mode boundaries are found and also plotted in the output plane. The output equation for the main mode is shown to be hyperbolic. Peak voltages are shown to be less than or equal to the input voltage, and peak currents are shown to be less than those of the frequency-controlled diode-clamped series resonant converter over a large operating range. A design procedure is given in the form of a design example. Data from a prototype converter is plotted with theoretical data in the output plane and good agreement with the theoretical model is obtained.

A buck converter with a given output filter is operated with pulse-width modulated and quasi-resonant switching schemes at the same nominal load and switching frequency. Electromagnetic interference generated by the natural switching action of the converter is examined by Fourier spectral analysis. Interference caused by excitation of parasitic elements is examined experimentally. Quasi-resonant converters are found to have a lower switching frequency harmonic bandwidth than the equivalent pulse-width modulated converter. The most significant parasitic responses are the turn-on current and turn-off voltage of the catch diode, and the gate charge current of the MOSFET switch. A significant decrease in radiated and conducted noise is obtained when the gate drive voltage rise and fall times are increased, which is possible without loss of efficiency using quasi-resonant switching.

As VLSI chip sizes and packing densities continue to escalate, electromigration failures have become a primary reliability concern. The issues concerning electromigration testing are addressed and an effective test for characterizing electromigration failures is presented. It is shown that this test is a reliable and sensitive measure for determining electromigration resistance based upon the construction of an electromigration database using this test. Lastly, the implementation of an electromigration process control test based upon the characterization is discussed.

The gain-bandwidth (GB) product of an operational amplifier (op amp) can effect the filtering characteristics of an infinite gain, multiple feedback, low pass active RC filter. In this thesis, the characteristics of ideal op amps and actual op amps are compared. The op amp is characterized by a dominant single pole, which is used to develop a third order voltage transfer function that describes the op amp's gain-bandwidth effects on the filter. Optimization theory is used to find adjusted values for the filter's elements to compensate for these GB effects. Of the sixty-five compensation design methods examined with the optimization program GOSPEL, twelve methods produced useful compensation results. The adjusted element values are tabulated and displayed in design graphs for several values of GB and quality factor, Q. The twelve design techniques were verified by simulating the filter with the adjusted element values using PSpice.

Optical matched filters have been used for the recognition of patterns in a noisy background. Different types of matched filters have been proposed since the introduction of the VanderLugt matched spatial filter. A novel filter, the hybrid phase-only matched filter, is proposed which shows promise for better signal to noise ratio, correlation peak intensity and light efficiency compared to the recently proposed optimal phase-only filter. A neural technique for the design of space-domain binary filter for pattern recognition applications is developed. The method takes advantage of the similarity in the structure of the minimum squared error criterion for the construction of linear discriminant functions and the Lyapunov function of the Hopfield Neural Model.

In evaluating the BER for direct sequence spread spectrum multiple-access communication systems, it is very difficult to obtain a closed form expression for the output of these systems. Therefore one usually resort to simulation techniques such as the Monte Carlo method to evaluate the BER. The BER is usually small for these systems, hence an excessive amount of time and computations is required to adequately estimate the BER. One way to circumvent this problem is to utilize importance sampling method, which will give a good estimate for the BER with relatively small number of simulation runs. A technique known as quick simulation method developed from the principles of large deviation theory and importance sampling is used to estimate the BER. The quick simulation method is compared to two other methods used to evaluate the BER.

Performance analysis of optical heterodyne receivers in Wavelength Division Multiplexing (WDM) has been an important research area in the last few years. WDM can potentially provide hundreds of Gb/s channels in the same fiber. However, because of channel interference in WDM, performance analysis is important to design the system properly. In this thesis, a detailed noise and jitter analysis has been performed for an optical heterodyne PSK receiver used in WDM. In WDM, noise sources include shot noise, channel interference noise, and phase noise. These noise sources will not only add to the signal, but also cause timing jitter at the bit timing recovery. Expressions for the noise and jitter variances at the detector input are derived for both RZ and NRZ signals. Bit error probabilities as a function of WDM channel separation are computed. It is found that the overall bit error rate performance of RZ is better than NRZ.

A hardware system for investigating Intersymbol Interference (ISI) in an optical data storage system has been designed and constructed by the author. The system consists of a pattern generator which produces data patterns of variable lengths and bit rates to be recorded on the optical disk. Data marks of the readback signal are quantized by a light-speed clock-counter system, and transferred in parallel to a personal computer for analysis. SNR values for collected data are obtained by computing mark size deviations of the readback signal from the original marks. A pseudo-random pattern of 31 bits is used for calculating SNR values for different spot sizes. Finally, Additive Interleaving Detection (AID) technique is implemented to compute another set of SNR values. 3-5db SNR improvement is observed when AID technique is used.

Signal delay estimates for high-speed interconnection nets are formulated using analytical methods. The equations are suitable for estimating delay in interconnects of printed wiring boards and multi-chip modules where the resistance of wires is small. Effects of drivers, receivers, chip interfaces and wires on delay are considered by using simple models. The wires are treated as lossless transmission lines with capacitive discontinuities modeling receiver chip interfaces. Drivers are voltage sources with series resistance. Signal delay consists of line propagation delay and delay due to the change in rise time and reflections at the discontinuities. Various commonly used net topologies are identified and wiring rules and delay predictors provided for each of them. It is shown that interconnect delay can be formulated as a non-linear function of the product of the line characteristic impedance and load capacitance. SPICE simulations are sued to validate analytical derivations.