Since the profitability of VLSI industries is related to yield, the IC manufacturer finds it highly desirable to be able to predict the yield by computer-aided methods. A key part in the procedure to obtain yield by computer simulation is to find the critical area of a layout. This thesis is primarily devoted to the calculations of critical area. There are two techniques to find the critical area. In the first technique, an analytic method was used to analyze the circuit geometry in order to find the critical area. In the second technique a Monte Carlo Method is used. A program using this Monte Carlo yield simulation (the main method used in this thesis) has been developed for determining critical area of the metal layer of a 4K random access memory. The analytic method is used in a supporting way. The thesis also proposes an easy method to process the vast amount of layout database. This method reduces the time consumed by Monte Carlo simulation.

This MS thesis proposes a methodology to compute a frequency dependent current distribution for a ground plane with the ultimate aim of utilizing this current distribution to compute the plane parasitics. A iterative finite differencing technique is utilized to solve a two dimensional diffusion equation for the current distribution on the plane. Starting with an initial DC current density over the entire plane grid, the frequency dependent current density is obtained by imposing the necessary boundary conditions and allowing the current to redistribute itself over the plane. An iterative procedure based on simultaneous over relaxation is employed to get faster convergence. This method takes into account the presence of sources, sinks and holes on the plane. Finally the plane parasitics are computed using integral methods and energy considerations.

The effects of high field stress on interface trap densities (Dit in MOS transistors are compared using three methods: charge-pumping, subthreshold swing and 1/f noise. The experimental MOS devices subjected to high field stress originated from two wafer lots processed with different concentrations of copper in the buffered oxide etchant. For the charge-pumping and subthreshold methods, no dependency is found on stress current polarity, wafer lot or transistor type (n- or p-channel). These two methods yield similar Dit values. For the 1/f noise method, no dependency is found on current polarity or wafer lot. However, the noise in the n-channel devices increases by several orders of magnitude as compared to the p-channel devices. A large discrepancy is found between Dit calculated from 1/f noise when compared to charge-pumping/subthreshold swing results for n-channel transistors. For p-channel transistors, the 1/f Dit results are in much better agreement with the results of the other two methods.

Three metal compositions are patterned via plasma etching into comb structures. The comb structures have pitches of 4 μm, 5 μm, 7 μm and 12 μm, with a line width of 2 μm, on a field oxide of 8,000 Angstroms thickness, using <111> p-type substrates. These comb test structures have been used to determine the number of bridges, and thus the yield, of the metal compositions: pure aluminum, silicon(2%)-aluminum, and copper(0.5%)-silicon(2%)-aluminum. Bridge failures are photographed and classified according to the source of the defect. The defects due to plasma particles are used to determine a yield model for this etch process. Through the use of yield model and test structure data the etch process is evaluated for the different metal systems. This allows a quantitative comparison of the systems in terms of defect clustering, defect density and defect size distribution, and hence projections for the best yielding process via the yield model.

In this thesis, a computer simulation has been done to evaluate the wavelength chirping and pulse broadening effects induced by the direct intensity modulation using Distributed Feedback (DFB) laser diodes. In the simulation, a DFB laser diode is driven by either square wave current pulses or pulses with a small current Step in the Leading Edge (SLE). A comparative study is performed to justify the effectiveness of using SLE waves in modulation to reduce wavelength chirping and pulse broadening. Numerical results from the single-mode rate equations show that the SLE wave modulation reduces the wavelength chirping and pulse broadening by a factor of 2. The optimal SLE pulse has a prepulse duration of 0.15 ns and a prepulse current level of 70.0 mA.

Output impedance matching for transmission line drivers is not easy to implement due to unavoidable process tolerances. An automatic system for adjusting the output impedance of fast CMOS drivers, on one chip, is described. The output impedance of all identical drivers is adjusted to match the impedance at the input of a reference transmission line, equal in geometry to the lines connected to the other drivers, by a circuit for measuring and correcting the mismatch between the output impedance of one of the drivers, taken as reference and dedicated for this purpose. The voltage measured at the far end of the reference line is sent to a differential amplifier where it is compared with the supply voltage of the final driving stage. According to the comparison result at specific time intervals, a signal is supplied to the regulator which supplies power to the penultimate driving stage, thereby controlling the resistance of the driver to match the line impedance. Simulations have shown that the percentage deviations of the far-end line voltage is approximately 3% for this design compared to a system without feedback which has a far-end line voltage deviation of approximately 18%.

The primary aim of the thesis is to determine the spectrum efficiency and power penalty of multi-level Subcarrier Multiplexing (SCM) transmission. To perform quantitative analysis, this thesis first develops a fiber transmission model. When there is one SCM transmission channel, it is found that the power penalty due to multi-level is 5 dB per bit at the same bit error rate (BER). For multiple channel SCM transmission, to reduce adjacent channel interference (ACI), it is found that binary transmission has the best spectrum efficiency for Non-Return-to-Zero (NRZ) pulses at the same BER. However, if raised-cosine pulses are used, 32-ary transmission is found to be the most efficient in spectrum use because of the smaller ACI.

This thesis presents a discrete time implementation and analysis of the generalized impulse response model proposed by Altes. This model is a generalization of the weighted sum of time delayed delta functions typically used to describe the impulse response of scattering targets. The target chosen for the analysis is the rigid acoustic sphere. The coefficients of the generalized model are used to calculate estimates of the radius of the sphere, which is known in advance for testing purposes. The accuracy of the radius estimates indicates the accuracy of the model coefficients. The generalized model is shown to be superior from the standpoint of radius estimation. An estimator for the time of arrival of a signal of unknown but deterministic form is derived. It is based upon a generalized likelihood ratio test whose structure accommodates the generalized model. This estimator performs well in high levels of noise.

The minority carrier generation lifetime is a parameter of central importance in the characterization, design, and operation of solid state devices. Various methods have been described for measuring the lifetime using an MOS capacitor (MOS-C). They can be classified according to the kind of voltage applied, the quantities measured, and the required elaboration of experimental results. This thesis discusses two groups of methods for determining the lifetime using an MOS-C: pulsed voltage methods and voltage sweep methods. The objective of this thesis is to give a comprehensive review and comparison of various methods for determination of minority carrier lifetime using an MOS-C. To accomplish this objective, the theory is presented as it exists in each respective reference, and the experiment is conducted based on the theory. Sometimes the theory is modified to include effects not considered in the original reference.

The electrical properties (resistance, capacitance, and inductance) of spherical solder bumps are computed. The solder bump is modeled using a finite, lossless transmission line model. The resistive, capacitive, and inductive effects are calculated separately then combined using superposition. The transmission line impedance for a 300 μm solder bump is calculated and the effect on a 100 nsec rise time signal is computed. Several methods to calculate fatigue lifetime are examined then related to reliability and design parameters. Methods to improve reliability are examined and their impact on electrical performance discussed.