Magister Commercii - MCom / This study investigates the effect of public debt on economic growth in South Africa since 1961-2017. Public debt stock is disaggregated into external debt and domestic debt in order to determine the effect of each on economic growth independently. The study employed the ARDL bound test to estimate the long and short run relationship among several macroeconomic variables - real economic growth, domestic debt, external debt, budget deficit, inflation rate and investment. An error correction model was used to analyses the short-run disequilibrium. The results show that there is a short and long run equilibrium relationship between foreign debt, domestic debt, budget deficit, inflation rate and economic growth. The empirical results indicate that external debt negatively affects the real GDP growth in South Africa, both in the short and long-run. Several policy implications emerged from the empirical results. To keep public debt more manageable, South Africa should improve its debt management. Furthermore, the country can make use of debt to equity swaps by privatizing underperforming parastatals. This would make them competitive and efficient.

Shrinking minimum feature size in deep sub-micron has made fabrication of progressively faster devices possible. The performance of interconnects has been a bottleneck in determining the overall performance of a chip. A reliable high-speed communication technique is necessary to improve the performance of on-chip communication. Recent publications have demonstrated that use of multiple threshold voltages improves the performance of a bus significantly. The multi-threshold capture mechanism takes advantage of predictable temporal behavior of a tightly coupled bus to predict the next state of the bus early. However, Use of multiple threshold voltages also reduces the voltage slack and consequently increases the susceptibility to noise. Reduction in supply voltage exacerbates the situation. This work proposes a novel error detection and correction encoding technique that takes advantage of the high performance of the multi-threshold capture mechanism as well as its inbuilt redundancy to achieve reliable high-speed communication while introducing considerably less amount of redundancy as compared to the conventional methods. The proposed technique utilizes graph-based algorithms to produce a set of valid code words. The algorithm takes advantage of implicit set operations using binary decision diagram to improve the scalability of the code word selection process. The code words of many crosstalk avoidance codes including the proposed error detection and correction technique exhibit a highly structured behavior. The sets of larger valid code words can be recursively formed using the sets of smaller valid code words. This work also presents a generalized framework for scalable on-chip code word generation. The proposed CODEC implementation strategy uses a structured graph to model the recursive nature of an encoding technique that facilitates scalable CODEC implementation. The non-enumerative nature of the implementation strategy makes it highly scalable. The modular nature of the CODEC also simplifies use of pipelined architecture thereby improving the throughput of the bus.

This work presents an energy efficient adaptive error correction system utilizing the Reed-Solomon errors-and-erasures algorithm, targeted to an Altera Stratix FPGA device. The system adapts to changing channel conditions by reconfiguring the system with different decoders to allow for the lowest possible energy consumption rate that the current channel conditions will allow. A series of energy saving optimizations were applied to a set of previous designs, resulting in a reduction in the energy required to decode a megabit of data of more than 70%. In addition, a new channel model was used to assess the effects of differing reconfiguration rates on codeword error rate, energy consumption, and decoding speed.

A modified, single error-correcting, and double error detecting Hamming code, hereafter referred to as modified SEC-DED Hamming code, is proposed in this research. The code requires fewer logic gates to implement than the SEC-DED Hamming code. Also, unlike the popular Hsiao's code, the proposed code can determine the error in the received word from its syndrome location in the parity check matrix. A detailed analysis of the area and power utilization by the encoder and decoder circuits of the modified SEC-DED Hamming code is also discussed. Results demonstrate that this code is an excellent alternative to Hsiao's code as the area and power values are very similar. In addition, the ability to locate the error in the received word from its syndrome is also of particular interest. Primitive polynomials play a crucial role in the hardware realizations for error-correcting codes. This research describes an implementation of a scalable primitive polynomial circuit with coefficients in GF(2). The standard cell area and power values for various degrees of the circuit are analyzed. The physical design of a degree 6 primitive polynomial computation circuit is also provided. In addition to the codes, a background of the already existing SPX GCD computation algorithm is provided. Its implementation revealed that the combinational implementation of the SPX algorithm utilizes a significantly lesser area than Euclid's algorithm. The FSMD implementation of the SPX algorithm reduces both dynamic and leakage power consumption. The physical design of the GCD computation using the SPX algorithm is also provided.

This thesis presents a new low complexity erasure decoder for staircase codes in optical interconnects between data centers. We developed a parallel software simulation environment to measure the performance of the erasure decoding techniques at output error rates relevant to an optical link. Low complexity erasure decoding demonstrated a 0.06dB increase in coding gain when compared to bounded distance decoding at an output error rate of 3 × 10⁻¹². Further, a log-linear extrapolation predicts a gain of 0.09dB at 10⁻¹⁵. This performance improvement is achieved without an increase in the maximum number of decoding iteration and keeping power constant. In addition, we found the optimal position within the decoding window to apply erasure decoding to minimize iteration count and output error rates, as well as the erasure threshold that minimizes the iteration count subject to the constrained erasure decoding structure.

During the thesis work, a feasibility study of the BPPM error-correction protocol is performed. The beyond pulse position modulation (BPPM) protocol was invented at Ericsson AB and describes a modulation encoding using vertically and horizontally polarized single photons for optical transmission and error-correction. The thesis work is a mixture of both experimental laboratory work and theoretical software simulations which are intended to mimic actual optical fiber transmission. One aspect of the project work involves designing the optical communication system which is used to evaluate the probabilities of transmission errors in the form of false detections and losses of light. During the project work, the BPPM protocol is implemented and used for software simulated error generation and correction. With the available laboratory setup used as the point of reference, error-correction using the BPPM protocol is studied using pulses of light containing more than one photon. The results show that the BPPM protocol can be used to recover some of the information that is lost during optical fiber transmission. Factors such as the size of the codewords, the number of photons per pulse and detection efficiency of the utilized single photon detector (SPD) have a significant impact on the success of the transmission.

yes / This article examines recent research in molecular communications from a telecommunications system design perspective. In particular, it focuses on channel models and stateof- the-art physical layer techniques. The goal is to provide a foundation for higher layer research and motivation for research and development of functional prototypes. In the first part of the article, we focus on the channel and noise model, comparing molecular and radio-wave pathloss formulae. In the second part, the article examines, equipped with the appropriate channel knowledge, the design of appropriate modulation and error correction coding schemes. The third reviews transmitter and receiver side signal processing methods that suppress intersymbol- interference. Taken together, the three parts present a series of physical layer techniques that are necessary to producing reliable and practical molecular communications. / The work of C.-B. Chae was in part supported by the Basic Science Research Program (2014R1A1A1002186) funded by the Ministry of Science, ICT and Future Planning (MSIP), Korea, through the National Research Foundation of Korea.

Tato diplomová práce se věnuje problematice VLSI návrhu a implementaci vrstvy RS-FEC pro 400 Gb/s Ethernet do FPGA Intel® Stratix® 10 DX 2100. V práci je charakterizován současný stav rychlostí Ethernetu, význam a kontext samoopravných kódů v rámci protokolu Ethernet. Dále je popsána výroba PLD čipů i matematická podstata RS sa moopravných kódů. V části praktické je představen návrh řešení systému RS-FEC, který byl realizován genericky pomocí jazyka VHDL. Zároveň byly jeho komponenty implementovány a v závěrečné diskusi je popsáno jeho řešení, dosažené výsledky včetně jeho budoucího rozšíření.

The Forest Resource Conservation and Shortage Relief Act of 1990 was the first federal attempt to impose a blanket restriction on export of roundwood to conserve existing forest cover and generate economic benefits from exporting processed wood. This study estimates the export demand equation for total export from United States Pacific Northwest, major species and destination countries using Johansen multivariate time series analysis. Cointegration rank is identified using Johansen cointegration test incorporating a structural breaks and normalized restriction is imposed to predict demand function under the framework of vector error correction model. All the variables under study are statistically significant with expected signs in the long run demand estimates. Roundwood export restriction policies are found to have impacted the export demand equation negatively. The study helps to understand the impact of log export restrictions policies along with other economic variables and assist in future policy formulations.

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