This thesis deals with network substandards from the TSN group (IEEE 802.1Q), which deal with prioritization of network traffic in TSN networks. These sub-standards include 802.1QBV and 802.1QBU, which have been described in more detail and compared in terms of network permeability and latency. Substandard 802.1QBU was chosen for the design implementation in FPGA. The design was described in VHDL. The designed design was verified by simulations, using self-tests. The work includes synthesis and time analysis.

This thesis deals with network substandards from the TSN group (IEEE 802.1Q), which deal with prioritization of network traffic in TSN networks. These sub-standards include 802.1QBV and 802.1QBU, which have been described in more detail and compared in terms of network permeability and latency. Substandard 802.1QBU was chosen for the design implementation in FPGA. The design was described in VHDL. The devloped design was verified by simulations, using self-tests. The work includes synthesis and time analysis.

The performance of the virtual switch Open vSwitch (OVS) is insufficient to satisfy the current requirements for link bandwidth of the server connections. There is an effort to accelerate the OVS both in the software and in the hardware by offloading the datapath to the smart network interface cards. In this work the COMBO card for 100G Ethernet developed by CESNET is used to accelerate the OVS. The suggested solution utilizes the firmware for FPGA generated from the definition in the P4 language to classify the packets in the card and DPDK for the data transfers and offloading the classification rules into the card. Forwarding of one flow with the shortest frames from physical to physical interface using one CPU core reaches forwarding rate of 11.2 Mp/s (10 times more than the standard OVS) with classification in the card and 5.9 Mp/s without classification in the card.

The aim of this work is to design digital synthesizer and modulator on embedded sys- tems. Work is exploring existing digital synthesizer and modulators in embedded systems and PC and with that gained knowledge is presenting possible solution of design on Field Programmable Gate Array.

This diploma thesis is about using vector control (or field-oriented control) of synchronous BLDC and PMSM motors on FPGAs. First part describes basic theory of these motors and how to control them. Then vector control is detailed and its parts as (or Clarke) and Park transformation. Rest of the thesis deals with the design of universal controller with adjustable accuracy in VHDL language. Data is separated from computing part which utilizes custom arithmetic-logic unit. In the last part of the thesis the design is tested in simulator using model of PMSM motor.

This semestral work deals with the design and realization of multipurpose milling machine for production of prototype small components made from soft materials and PCBs. Thesis contains design of mechanical construction, individual parts of driving machine and graphic user interface.

Master thesis is dealing with issues and problems of packet queue management in high speed packet networks. Design implementation is made in VHDL hardware description language. In theoretical part of thesis are explained different types of mechanism used for providing quality of service in communication networks. Furthermore the brief description o VHDL, FPGA and framework Netcope Development Kit is a piece of theoretical part as well. The outcome of practical part contains a design, limiting packet queues based on Tocken Bucket mechanism. Design verification was made by simulations, synthesis and real implementation on smart NIC NFB-200G2QL. All kind of verificaion results are summerized in last three chapters.

This thesis deals with possible and realized decompression and playing of video on platforms, using FPGA unit. For implementation of this player is used platform FITKit, which has integrated VGA connector and large enough RAM memory. It uses a hard drive as memory medium with FAT32 file system.

Cílem této práce je seznámení se s problematikou detekce ionizujícího záření a jeho detekcí zejména pomocí proporcionálních detektorů a navrhnutí algoritmu pro jejich klasifikaci a jeho následná implementace do FPGA. V první části práce je obecně popsáno, jak jednotlivé typy plynem plněných detektorů fungují. V druhé části je věnován prostor algoritmům pro klasifikaci pulzů, které se objevují v literatuře. Následuje návrh vlastního algoritmu, jeho rozbor a rozebrání výsledků. Ve třetí části následuje popis samotné realizace navrhnutého řešení na platformě RedPitaya. Je zde rozebrána celková architektura navrhnutého systému, detailně popsány jak jednotlivé bloky v logice FPGA, tak i ostatní skripty zajišťující zpracování naměřených výsledků a jejich vizualizaci.

This paper describes implementation of the whole cryptographic protocol TLS including control logic and used cryptographic systems. The goal is to implement an application in the FPGA technology, so it could be used in hardware accelerated network card. The reason for this is new supported higher transmission speeds that Ethernet is able to operate on, and the absence of implementation of this protocol on FPGA. In the first half of this paper is described theory of cryptography followed by description of TLS protocol, its development, structure and operating workflow. The second half describes the implementation on the chosen technology that is also described here. It is used already existing solutions of given cryptographic systems for the implementation, or at least their parts that are modified if needed for TLS. It was implemented just several parts of whole protocol, such are RSA, Diffie-Hellman, SHA and part of AES. Based on these implementations and continuing studying in this matter it was made conclusion, that FPGA technology is inappropriate for implementation of TLS protocol and its control logic. Recommendation was also made to use FPGA only for making calculations of given cryptographic systems that are controlled by control logic from software implemented on standard processors.