Asymmetric multiprocessing (AMP) is a way of distributing computer system load toheterogeneous hardware and software environment. This thesis describes the principles of the AMP focusing on the ARM Cortex--A9 processor and Altera Cyclone V hardware platform. Development of a OpenAMP framework based AMP system showing communication among the processor cores, documentation and future work suggestion are the products of this thesis.

The goal of the thesis is to design a development board that may be used for embedded systems prototyping. The board's key parts are an ARM-Cortex-based microcontroller and a FPGA programmable circuit. The platform is designed with .NET Micro Framework support in mind. The thesis contains specifications of the development board, describes the design process as well as the task of .NET Micro Framework porting and the establishment of communication bus between the FPGA and microcontroller circuits. The thesis is concluded by a set of demonstration examples which outline how to develop new applications for the designed platform.

Embedded systems are dedicated to perform specific tasks, so design engineers can optimize them to reduce the size and cost of the product and increase the reliability and performance. However, result of these optimizations is that some architectures may lack commonly used technologies such as direct memory access (DMA). We may encounter with this situation in family of microcontrollers HCS08. The main theme of this work is to describe a design of DMA controller that can be added into the family of microcontrollers HCS08.

This thesis describes the requirements analysis, design and implementation of stateful packet filtering to an existing stateless firewall. They also deals with testing of the implemented system. The first two chapters describe the properties NetCOPE development platform for FPGA. They also describes the principle of operation           firewall, which also serves as a requirements specification for stateful firewall. Then describes the detailed design of individual modules to modify the existing firewall and the proposal for the creation of new modules. It also discusses the implementation of the proposed modules and testing for proper operation. Finally, it discuss the current state of the thesis and describes possible future expansion.

This masters thesis deals with design of the component facilitating communication between PCI bus and user component. Designed component is simplifying the communication protocol between designed and user components, while advanced functions of PCI bus are preserved. Target platform is COMBO6-PTM card containing FPGA with Spartan 3 technology. Communication with PCI bus is mediated by PLX component. Thesis also contains design of simplified communication protocol.

Funkční verifikace je jednou z nejrozšířenějších technik ověřování korektnosti hardwarových systémů podle jejich specifikace. S nárůstem složitosti současných systémů se zvyšují i časové požadavky kladené na funkční verifikaci, a proto je důležité hledat nové techniky urychlení tohoto procesu. Teoretická část této práce popisuje základní principy různých verifikačních technik, jako jsou simulace a testování, funkční verifikace, jakož i formální analýzy a verifikace. Následuje popis tvorby verifikačních prostředí nad hardwarovými komponentami v jazyce SystemVerilog. Část věnující se analýze popisuje požadavky kladené na systém pro akceleraci funkční verifikace, z nichž nejdůležitější jsou možnost jednoduchého spuštění akcelerované verze verifikace a časová ekvivalence akcelerovaného a neakcelerovaného běhu verifikace. Práce dále představuje návrh verifikačního rámce používajícího pro akceleraci běhů verifikace technologii programovatelných hradlových polí se zachováním možnosti spuštění běhu verifikace v uživatelsky přívětivém ladicím prostředí simulátoru. Dle experimentů provedených na prototypové implementaci je dosažené zrychlení úměrné počtu ověřovaných transakcí a komplexnosti verifikovaného systému, přičemž nejvyšší zrychlení dosažené v sadě experimentů je více než 130násobné.

This term project focuses on algorithms for pattern matching used in modern IDS. The main focus is on regular expression matching. It deals with methods based on deterministic and nondeterministic finite automata, hybrid methods and with method based on regular expressions as programing langue for specialised processors. Implementation of pattern matching units based on some of described methodologies is described in next part. Methodology for resource consumption estimation is also described. Developed software system for unit generation is described in the next part. In the final part results are presented and discused.

This master's thesis deals with design of simple embedded system based on Atmel ARM. There are Atmel's products covering this market segment reviewed in the first part, including the description of a couple of devices. The second part is focused on the aim specification, selection of components, their interconnection, power-supply requirements, price considerations and the design itself. The next chapter describes testing and application of the platform. The conclusion presents the current state of the project and deals with the successive progress.

Genetic information of all living organisms is stored in DNA. Exploring of its structure and function represents an important area of research in modern biology. One of the interesting structures occurring in DNA are palindromes. Based on the research they are expected to play an important role in interpreting the information stored in DNA, because they are often observed near important genes. Palindromes searching is complicated by the presence of mutations (changes in sequences of DNA elements), which increases the time complexity of algorithms. Therefore it is reasonable to study their parallelization and acceleration. The objective of this work is a study of palindromes searching methods and acceleration architecture design. The hardware unit implemented in a chip with FPGA technology placed on ml555 board can speed up the calculation up to 6 667 times in comparison with the best-known software method relying on suffix arrays.

This thesis is about unusal view of implementation of graphic algorithms in FPGA in computer vision context. There are some informations about raster image and raster image operations, raster image segmentation usign threhsholding and adaptive thresholding and FPGA and DSP platforms. Next, there is a concept of the concrete project realization in the Unicam2D camera and description other ways of implementation. Next, there is a description of implemented tests with some demonstration followed by discussion of ressults in the end of the work.