In this thesis a method to compensate camera distortion is developed for an FPGA platform as part of a complete vision system. Several methods and models is presented and described to give a good introduction to the complexity of the problems that is overcome with the developed method. The solution to the core problem is shown to have a good precision on a sub-pixel level.

The computer vision problem of object tracking is introduced and explained. An approach to interest point based feature detection and tracking using FAST and BRIEF is presented and the selection of algorithms suitable for implementation on a Xilinx Zynq7000 with an XC7Z020 field-programmable gate array (FPGA) is detailed. A modification to the smoothing strategy of BRIEF which significantly reduces memory utilization on the FPGA is presented and benchmarked against a reference strategy. Measures of performance and resource efficiency are presented and utilized in an iterative development process. A system for interest point based object tracking that uses FAST for feature detection and BRIEF for feature description with the proposed smoothing modification is implemented on the FPGA. The design is described and important design choices are discussed.

Random number generators are basic building blocks of modern cryptographic systems. Usually pseudo random number generators, carefully constructed deter- ministic algorithms that generate seemingly random numbers, are used. These are built upon foundations of thorough mathematical analysis and have been subjected to stringent testing to make sure that they can produce pseudo random sequences at a high bit-rate with good statistical properties. A pseudo random number generator must be initiated with a starting value. Since they are deterministic, the same starting value used twice on the same pseudo random number generator will produce the same seemingly random sequence. Therefore it is of utmost importance that the starting value contains enough en- tropy so that the output cannot be predicted or reproduced in an attack. To gen- erate a high entropy starting value, a true random number generator that uses sampling of some physical non-deterministic phenomenon to generate entropy, can be used. These are generally slower than their pseudo random counterparts but in turn need not generate the same amount of random values. In field programmable gate arrays (FPGA), generating random numbers is not trivial since they are built upon digital logic. A popular technique to generate entropy within a FPGA is to sample jittery clock signals. A quite recent technique proposed to create a robust clock signals, that contains such jitter, is to use self- timed ring oscillators. These are structures in which several events can propagate freely at an evenly spaced phase distribution. In this thesis self-timed rings of six different lengths is implemented on a spe- cific FPGA hardware. The different implementations are tested with the TestU01 test suite. The results show that two of the implementations have a good oscilla- tory behaviour that is well suited for use as random number generators. Others exhibit unexpected behaviours that are not suited to be used in a random num- ber generator. Two of the implemented random generators passed all tests in the TestU01 batteries Alphabit and BlockAlphabit. One of the generators was deemed not fit for use in a random number generator after failing all of the tests. The last three were not subjected to any tests since they did not behave as ex- pected.

Fog and haze can have a dramatic impact on vision systems for land and sea vehicles. The impact of such conditions on infrared images is not as severe as for standard images. By fusing images from two cameras, one ordinary and one near-infrared camera, a complete dehazing system with colour preservation can be achieved. Applying several different algorithms to an image set and evaluating the results, the most suitable image fusion algoritm has been identified. Using an FPGA, a programmable integrated circuit, a crucial part of the algorithm has been implemented. It is capable of producing processed images 30 times faster than a laptop computer. This implementation lays the foundation of a real-time dehazing system and provides a significant part of the full solution. The results show that such a system can be accomplished with an FPGA.

Ce manuscrit présente les travaux menés pour proposer un flot de conception permettant d’implanter des processeurs RISP dans un circuit reprogrammable (FPGA). Après une description des différentes solutions envisageables pour réaliser des prototypes dans le domaine du traitement d’image, ce document décrit une méthode qui consiste à générer des modèles matériels de processeurs destinés au traitement d’images, avec des opérateurs taillés sur une application donnée. Un ensemble d’expérimentations utilisant des algorithmes courants permet d’évaluer les performances du flot de conception proposé. Le prototypage rapide d’un système biométrique sans contact, basé sur la reconnaissance de paumes a été aussi réalisé sur la plateforme de test. / This manuscript presents work to propose a development cycle to establish RISP processors in a reprogrammable chip (FPGA). After a description of the various possible solutions to produce image processing prototypes, this document describes a method which consists in generating hardware models of processor target to image processing, with operators just for a given application. Test with a set of common algorithm makes evaluate the performances of the design cycle proposed. Rapid prototyping of a contact less biometric system, based on palmprint recognition, is also realized on the test platform.

Ce travail s'attaque à la mise en évidence expérimentale d'effets quantiques dans le mouvement d'un résonateur mécanique macroscopique avec une masse effective de 33 microgrammes, soit 3 ordres de grandeur au-dessus de celle du système mécanique le plus massif observé à ce jour dans son état quantique fondamental. Nous avons conçu, fabriqué et fait fonctionner un résonateur optomécanique à 3,6 MHz avec une finesse optique de 100.000 et un facteur de qualité mécanique proche de 100 millions, inséré dans l'environnement à 100 mK d'un réfrigérateur à dilution. Nous présentons un montage optique complètement automatisé incluant une cavité de filtrage, une détection homodyne et plusieurs asservissements, implémentés dans un FPGA avec le programme PyRPL développé spécifiquement pour cette expérience. Nous avons refroidi par laser le mode de compression de notre résonateur mécanique jusqu'à un nombre moyen d'occupation thermique de 20 phonons. Le refroidissement est limité par l'apparition d'une instabilité optomécanique de plusieurs modes des suspensions, au-dessous de 100 kHz. Un filtre digital particulier pour supprimer cette instabilité nous a permis d'atteindre le régime où l'action en retour quantique contribue à hauteur d'environ 30 % au bruit de force total de l'oscillateur mécanique. Pour atteindre des contributions encore plus importantes à l'avenir, nous présentons la conception d'un miroir d'entrée à cristal phononique, caractérisé par un plancher de bruit de mouvement Brownien réduit. / In this work, we attempt the experimental demonstration of quantum effects in the motion of a macroscopic mechanical resonator with a mass of 33 micrograms, about 3 orders of magnitude above the mass of the heaviest system demonstrated so far in the quantum ground state. We have designed, fabricated, and operated an optomechanical resonator at 3.6 MHz, with an optical finesse of 100,000 and a mechanical quality factor near 100 million, embedded in the 100 mK environment of a dilution refrigerator. We present a fully automatized optical measurement setup, including a filter cavity, a homodyne detector, and various feedback controllers implemented in an FPGA with the custom-developed software PyRPL. We have laser-cooled the compression mode of our mechanical resonator to a mean thermal occupation number of 20 phonons. Cooling is limited by the onset of an optomechanical instability of suspension modes with frequencies below 100 kHz. A custom-tailored digital filter to suppress this instability has enabled us to reach a regime where quantum backaction amounts to about 30 % of the total force noise on the mechanical resonator. For even higher ratios in the future, we present the design of a phononic-crystal input mirror with a reduced Brownian motion displacement noise floor.

Depuis une vingtaine d'années, le GRAMS et le CIMS travaillent en collaboration dans le domaine de l'imagerie médicale, plus précisément sur la tomographie d'émission par positrons destinée à la recherche préclinique sur petits animaux. Après le scanner TEP Sherbrooke en 1994 et le LabPET I commercialisé par Advanced Molecular Imaging (AMI) Inc., Gamma Medica Ideas et GE Healthcare au cours des années 2000, l'aspiration vers de meilleures performances est le moteur de la réalisation d'une nouvelle version : le LabPET II. L'augmentation importante du nombre de détecteurs, nécessaire pour atteindre une meilleure résolution spatiale, amène de nouveaux défis autant sur le plan matériel que logiciel. Un des défis est de compenser les disparités en gain des détecteurs à base de photodiodes à avalanche (PDA) qui engendrent des différences intercanaux. Le but de ce projet de maîtrise est de développer et d'implémenter un algorithme capable de corriger ces différences de façon automatisée.

Reverse-engineering the brain is one of the US National Academy of Engineering’s “Grand Challenges.” The structure of the brain can be examined at many different levels, spanning many disciplines from low-level biology through psychology and computer science. This thesis focusses on real-time computation of large neural networks using the Izhikevich spiking neuron model. Neural computation has been described as “embarrassingly parallel” as each neuron can be thought of as an independent system, with behaviour described by a mathematical model. However, the real challenge lies in modelling neural communication. While the connectivity of neurons has some parallels with that of electrical systems, its high fan-out results in massive data processing and communication requirements when modelling neural communication, particularly for real-time computations. It is shown that memory bandwidth is the most significant constraint to the scale of real-time neural computation, followed by communication bandwidth, which leads to a decision to implement a neural computation system on a platform based on a network of Field Programmable Gate Arrays (FPGAs), using commercial off- the-shelf components with some custom supporting infrastructure. This brings implementation challenges, particularly lack of on-chip memory, but also many advantages, particularly high-speed transceivers. An algorithm to model neural communication that makes efficient use of memory and communication resources is developed and then used to implement a neural computation system on the multi- FPGA platform. Finding suitable benchmark neural networks for a massively parallel neural computation system proves to be a challenge. A synthetic benchmark that has biologically-plausible fan-out, spike frequency and spike volume is proposed and used to evaluate the system. It is shown to be capable of computing the activity of a network of 256k Izhikevich spiking neurons with a fan-out of 1k in real-time using a network of 4 FPGA boards. This compares favourably with previous work, with the added advantage of scalability to larger neural networks using more FPGAs. It is concluded that communication must be considered as a first-class design constraint when implementing massively parallel neural computation systems.

In this thesis we present pvFPGA, the first system design solution for virtualizing an FPGA - based hardware accelerator on the x86 platform. The accelerator design on the FPGA can be used for accelerating various applications, regardless of the application computation latencies. Our design adopts the Xen virtual machine monitor (VMM) to build a paravirtualized environment, and a Xilinx Virtex - 6 as an FPGA accelerator. The accelerator communicates with the x86 server via PCI Express (PCIe). In comparison to the current GPU virtualization solutions, which primarily intercept and redirect API calls to the hosted or privileged domain’s user space, pvFPGA virtualizes an FPGA accelerator directly at the lower device driver layer. This gives rise to higher efficiency and lower overhead. In pvFPGA, each unprivileged domain allocates a shared data pool for both user - kernel and inter-domain data transfer. In addition, we propose the coprovisor, a new component that enables multiple domains to simultaneously access an FPGA accelerator. The experimental results have shown that 1) pvFPGA achieves close-to-zero overhead compared to accessing the FPGA accelerator without the VMM layer, 2) the FPGA accelerator is successfully shared by multiple domains, 3) distributing different maximum data transfer bandwidths to different domains can be achieved by regulating the size of the shared data pool at the split driver loading time, 4) request turnaround time is improved through DMA (Direct Memory Access) context switches implemented by the coprovisor.

This thesis investigates the use of massively parallel fine-grained processor arrays to increase computational performance. As processors move towards multi-core processing, more energy-efficient processors can be designed by increasing the number of processor cores on a single chip rather than increasing the clock frequency of a single processor. This can be done by making processor cores less complex, but increasing the number of processor cores on a chip. Using this philosophy, a processor core can be reduced in complexity, area, and speed to form a very small processor which can still perform basic arithmetic operations. Due to the small area occupation this can be multiplied and scaled to form a large scale parallel processor array to offer a significant performance. Following this design methodology, two fine-grained parallel processor arrays are designed which aim to achieve a small area occupation with each individual processor so that a larger array can be implemented over a given area. To demonstrate scalability and performance, SIMD parallel processor array is designed for implementation on an FPGA where each processor can be implemented using four ‘slices’ of a Xilinx FPGA. With such small area utilization, a large fine-grained processor can be implemented on these FPGAs. A 32 × 32 processor array is implemented and fast processing demonstrated using image processing tasks. An event-driven MIMD parallel processor array is also designed which occupies a small amount of area and can be scaled up to form much larger arrays. The event-driven approach allows the processor to enter an idle mode when no events are occurring local to the processor, reducing power consumption. The processor can switch to operational mode when events are detected. The processor core is designed with a multi-bit data path and ALU and contains its own instruction memory making the array a multi-core processor array. With area occupation of primary concern, the processor is relatively simple and connects with its four nearest direct neighbours. A small 8 × 8 prototype chip is implemented in a 65 nm CMOS technology process which can operate at a clock frequency of 80 MHz and offer a peak performance of 5.12 GOPS which can be scaled up to larger arrays. An application of the event-driven processor array is demonstrated using a simulation model of the processor. An event-driven algorithm is demonstrated to perform distributed control of distributed manipulator simulator by separating objects based on their physical properties.