Analytical modelling and characterization of Weighted Fair Queueing (WFQ) have recently received considerable attention by several researches since WFQ offers the minimum delay and optimal fairness guarantee. However, all previous work on WFQ has focused on developing approximations of the scheduler with an infinite buffer because of supposed scalability problems in the WFQ computation. The main aims of this thesis are to study WFQ system, by providing an analytical WFQ model which is a theoretical construct based on a form of processor sharing for finite capacity. Furthermore, the solutions for classes with Poisson arrivals and exponential service are derived and verified against global balance solution. This thesis shows that the analytical models proposed can give very good results under particular conditions which are very close to WFQ algorithms, where accuracy of the models is verified by simulations of WFQ model. Simulations were performed with QNAP-2 simulator. In addition, the thesis presents several performance studies signifying the power of the proposed analytical model in providing an accurate delay bounds to a large number of classes. These results are not able to cover all unsolved issues in the WFQ system. They represent a starting point for the research activities that the Author will conduct in the future. The author believes that the most promising research activities exist in the scheduler method to provide statistical guarantees to multi-class services. The author is convinced that alternative software, for example, on the three class model buffer case, is able to satisfy the large number of buffer because of the software limitation in this thesis. While they can be a good topic for long-term research, the short-medium term will show an increasing interest in the modification of the WFQ models to provide differentiated services.

Analytical modelling and characterization of Weighted Fair Queueing (WFQ) have recently received considerable attention by several researches since WFQ offers the minimum delay and optimal fairness guarantee. However, all previous work on WFQ has focused on developing approximations of the scheduler with an infinite buffer because of supposed scalability problems in the WFQ computation. The main aims of this thesis are to study WFQ system, by providing an analytical WFQ model which is a theoretical construct based on a form of processor sharing for finite capacity. Furthermore, the solutions for classes with Poisson arrivals and exponential service are derived and verified against global balance solution. This thesis shows that the analytical models proposed can give very good results under particular conditions which are very close to WFQ algorithms, where accuracy of the models is verified by simulations of WFQ model. Simulations were performed with QNAP-2 simulator. In addition, the thesis presents several performance studies signifying the power of the proposed analytical model in providing an accurate delay bounds to a large number of classes. These results are not able to cover all unsolved issues in the WFQ system. They represent a starting point for the research activities that the Author will conduct in the future. The author believes that the most promising research activities exist in the scheduler method to provide statistical guarantees to multi-class services. The author is convinced that alternative software, for example, on the three class model buffer case, is able to satisfy the large number of buffer because of the software limitation in this thesis. While they can be a good topic for long-term research, the short-medium term will show an increasing interest in the modification of the WFQ models to provide differentiated services. / Ministry of Higher Education

A scheduling algorithm has the primary role in implementing the quality of service guaranteed to each flow by managing buffer space and selecting which packet to send next with a fair share of network. In this thesis, some scheduling algorithms for packet switching networks are studied. For evaluating their delay, jitter and throughput performances, a discrete event simulator has been developed. It has been seen that fair scheduling provides, fair allocation of bandwidth, lower delay for sources using less than their full share of bandwidth and protection from ill-behaved resources.

La thèse s'intéresse à la réalisation d'une architecture de Qualité de Service en rupture avec les approches classiques, permettant d'offrir des garanties de bout en bout pour le trafic. L'approche Flow-Aware Networking considère le trafic au niveau des flux applicatifs, pour lesquels des modèles de trafic simples mais robustes conduisent à une relation fondamentale entre ressources offertes par le réseau, la demande générée, et la performance obtenue. En particulier, l'architecture de routeur Cross-Protect propose la combinaison d'un ordonnancement fair queueing et d'un contrôle d'admission afin d'assurer de manière implicite la performance des flots streaming et élastique, sans nécessiter ni marquage ni procotole de signalisation. Dans un tel contexte, nous considérons le dimensionnement des buffers au sein des routeurs, l'introduction d'un ordonnancement de type fair queueing dans le réseau et son impact sur la performance des protocoles TCP, ainsi que la réalisation d'un algorithme de contrôle d'admission approprié. Pour terminer, une déclinaison de cette architecture pour le réseau d'accès est proposée. / The thesis deals with the realization of a Quality of Service architecture that breaks with traditional approaches, and allows end-to-end performance guarantees for the traffic. The Flow-Aware Networking approach considers the traffic at the flow level, for which simple but robust traffic models lead to a fundamental relationship between the resources offered by the network, the demand and the obtained performance. In particular, the Cross-Protect router architecture proposes the combination of a fair queueing scheduler, and an admission control so as to implicitly ensure the performance of both streaming and elastic flows, without the need for any marking nor signalization protocol. In such a context, we consider the sizing of router buffers, the introduction of fair queueing scheduling inside the network and its impact on the performance of TCP protocols, as well as the realization of a suitable admission control algorithm. Finally, a declination of this architecture for the access network is proposed.