The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities.

A Field-Programmable Gate Array (FPGA) is a configurable platform for implementing a variety of logic circuits. It implements a circuit by the means of logic elements, usually Lookup Tables, connected by a programmable routing network. To utilize an FPGA effectively Computer Aided Design (CAD) tools have been developed. These tools implement circuits by using a traditional CAD flow, where the circuit is analyzed, synthesized, technology mapped, and finally placed and routed on the FPGA fabric. This flow, while generally effective, can produce sub-optimal results because once a stage of the flow is completed it is not revisited. This problem is addressed by an enhanced flow known Physical Synthesis, which consists of a set of iterations of the traditional flow with one key difference: the result of each iteration directly affects the result of the following iteration. An optimization can therefore be evaluated and then adjusted as needed in the following iterations, resulting in an overall better implementation. This CAD flow is challenging to work with because for a given FPGA researchers require access to each stage of the flow in an iterative fashion. This is particularly challenging when targeting modern commercial FPGAs, which are far more complex than a simple Lookup Table and Flip-Flop model generally used by the academic community. This dissertation describes a unified framework, called the Physical Synthesis Toolkit (PST), for research and development of optimizations for modern FPGA devices. PST provides access to modern FPGA devices and CAD tool flow to facilitate research. At the same time the amount of effort required to adapt the framework to a new FPGA device is kept to a minimum. To demonstrate that PST is an effective research platform, this dissertation describes optimization and modeling techniques that were implemented inside of it. The optimizations include: an area reduction technique for XOR-based logic circuits implemented on a 4-LUT based FPGA (25.3% area reduction), and a dynamic power reduction technique that reduces glitches in a circuit implemented on an Altera Stratix II FPGA (7% dynamic power reduction). The modeling technique is a novel toggle rate estimation approach based on the XOR-based decomposition, which reduces the estimate error by 37% as compared to the latest release of the Altera Quartus II CAD tool.

The complexity of Field-Programmable Gate Array (FPGAs) logic blocks have undergone constant evolution to the point where both the basic soft logic blocks that implement combinational logic and the fixed-function hard blocks contain complex interconnects, hierarchy and modes. The goal of this thesis is to both support that complexity and enable future architecture exploration of even increased complexity and new kinds of hard functionality. To accomplish this, a Computer-Aided Design (CAD) flow that can map a user circuit to an FPGA with these complex blocks is needed. We propose a new language that can describe these complex blocks and a new area-driven tool for the packing stage of that CAD flow. The packing stage groups components of a user circuit into the complex blocks available on the FPGA. We conduct experiments to illustrate the quality of the packing tool and to demonstrate the newly-enabled architecture exploration capabilities.

Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times during circuit operation, thereby reducing switching activity and lowering dynamic power. The concept is rooted in the property that under certain conditions, some signals within digital designs are not "observable" at design outputs, making the circuitry that generates such signals a candidate for guarding. Guarded evaluation has been demonstrated successfully for custom ASICs; in this work, we apply the technique to FPGAs. In ASICs, guarded evaluation entails adding additional hardware to the design, increasing silicon area and cost. Here, we apply the technique in a way that imposes minimal area overhead by leveraging existing unused circuitry within the FPGA. The LUT functionality is modified to incorporate the guards and reduce toggle rates. The primary challenge in guarded evaluation is in determining the specific conditions under which a sub-circuit's inputs can be held constant without impacting the larger circuit's functional correctness. We propose a simple solution to this problem based on discovering gating inputs using "non-inverting paths" and trimming inputs using "partial non-inverting paths" in the circuit's AND-Inverter graph representation. Experimental results show that guarded evaluation can reduce switching activity by as much as 32% for FPGAs with 6-LUT architectures and 25% for 4-LUT architectures, on average, and can reduce power consumption in the FPGA interconnect by 29% for 6-LUTs and 27% for 4-LUTs. A clustered architecture with four LUTs to a cluster and ten LUTs to a cluster produced the best power reduction results. We implement guarded evaluation at various stages of the FPGA CAD flow and analyze the reductions. We implement the algorithm as post technology mapping, post packing and post placement optimizations. Guarded Evaluation as a post technology mapping algorithm inserted the most number of guards and hence achieved the highest activity and interconnect reduction. However, guarding signals come with a cost of increased fanout and stress on routing resources. Packing and placement provides the algorithm with additional information of the circuit which is leveraged to insert high quality guards with minimal impact on routing. Experimental results show that post-packing and post-placement methods have comparable reductions to post-mapping with considerably lesser impact on the critical path delay and routability of the circuit.

In this thesis a microcontroller core is developed in an FPGA. Its instruction set is compatible with the microcontroller PIC16XX series by Microchip Technology. The microcontroller employs a RISC architecture with separate busses for instructions and data. Our goal in this research is to implement and evaluate the design in the FPGA. Increasing performance and gate capacity of recent FPGA devices permits complex logic systems to be implemented on a single programmable device. Such a growing complexity demands design approaches, which can lead to designs containing millions of logic gates, memories, high-speed interfaces, and other high-performance components. In recent years, the continuous development in the area of highly integrated circuits has lead to a change in the design methods used, making it possible to economically utilize FPGAs in many designs. A test demo board from the Digilent Inc is used to fit our testing requirements of the RISC microcontroller. The test demo board also had the capability of communicating with a personal computer (PC) so that we can load the program from PC. Based on the modern design methods the microcontroller core is developed using the Verilog hardware description language. Xilinx ISE Foundation 6.3i software is used for its synthesis and implementation. An embedded test program code using MPLAB is also developed, and then loaded into the designed microcontroller residing in the FPGA. In order to perform a functional test of the microcontroller core a special test program downloader application is designed by using Borland C++ Builder. First, the specification from the PIC16XX datasheet is transferred into an abstract behavioral description. Based on that, the next step is to develop a description of the microcontroller core with some minor modifications which can be synthesizable into a FPGA. Finally, the resulting gate level netlist is evaluated and tested using a demo board.

In this thesis, we address the problem of digital intellectual property (IP) protection for the field programmable gate array (FPGA) designs. Substantial time and effort is required to the design complex circuits; thus, it makes sense to re-use these designs. An IP developer can sell his design to the companies and collect royalty. However, he needs to protect his work from security breach and piracy. The legal means of IP protection such as patents and license agreements are a deterrent to illegal IP circulation, but they are insufficient to detect an IP protection breach. Watermarking provides a means to identify the owner of a design. Firstly, we propose a watermarking technique that modifies the routing of an FPGA design to make it a function of the signature text. This watermarking technique is a type of constraint-based watermarking technique where we add a signature-based term to the routing cost function. Secondly, we need a method to verify the existence of the watermark in the design. To address this we propose a digital signature generation technique. This technique uses the switch state (ON/OFF) of certain switches on the routing to uniquely identify a design. Our results show less than 10% speed overhead for a minimum channel width routing. Increasing the channel width by unit length, we could watermark the design with a zero speed overhead. The increase in the wire length is negative for majority of the circuits. Our watermarking technique can be integrated into the current routing algorithm since it does not require an additional step for embedding the watermark. The overall design effort for routing a watermarked design is equivalent to that of routing a non-watermarked design.

Neural simulations and general dynamical system modeling consistently push the limits of available computational horsepower. This is occurring for a number of reasons: 1) models are progressing in complexity as our biological understanding increases, 2) high-level analysis tools including parameter searches and sensitivity analyses are becoming more prevalent, and 3) computational models are increasingly utilized alongside with biological preparations in a dynamic clamp configuration. General-purpose computers, as the primary target for modeling problems, are the simplest platform to implement models due to the rich variety of available tools. However, computers, limited by their generality, perform sub-optimally relative to custom hardware solutions. The goal of this thesis is to develop a new cost-effective and easy-to-use platform delivering orders of magnitude improvement in throughput over personal computers. We suggest that FPGAs, or field programmable gate arrays, provide an outlet for dramatically enhanced performance. FPGAs are high-speed, reconfigurable devices that can implement any digital logic operation using an array of parallel computing elements. Already common in fields such as signal processing, radar, medical imaging, and consumer electronics, FPGAs have yet to gain traction in neural modeling due to their steep learning curve and lack of sufficient tools despite their high-performance capability. The overall objective of this work has been to overcome the shortfalls of FPGAs to enable adoption of FPGAs within the neural modeling community. We embarked on an incremental process to develop an FPGA-based modeling environment. We first developed a prototype multi-compartment motoneuron model using a standard digital-design methodology. FPGAs at this point were shown to exceed software simulations by 10x to 100x. Next, we developed canonical modeling methodologies for manual generation of typical neural model topologies. We then developed a series of tools and techniques for analog interfacing, digital protocol processing, and real-time model tuning. This thesis culminates with the development of Dynamo, a fully-automated model compiler for the direct conversion of a model description into an FPGA implementation.

Thesis (M.S.)--University of North Texas, Aug., 2007. / Title from title page display. Includes bibliographical references.

Thesis (M.Eng)--University of Wollongong, 2005. / Typescript. Includes bibliographical references: p. 169-170.

Thesis(M.S.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references.