A Field-Programmable Gate Array (FPGA) is a configurable platform for implementing a variety of logic circuits. It implements a circuit by the means of logic elements, usually Lookup Tables, connected by a programmable routing network. To utilize an FPGA effectively Computer Aided Design (CAD) tools have been developed. These tools implement circuits by using a traditional CAD flow, where the circuit is analyzed, synthesized, technology mapped, and finally placed and routed on the FPGA fabric. This flow, while generally effective, can produce sub-optimal results because once a stage of the flow is completed it is not revisited. This problem is addressed by an enhanced flow known Physical Synthesis, which consists of a set of iterations of the traditional flow with one key difference: the result of each iteration directly affects the result of the following iteration. An optimization can therefore be evaluated and then adjusted as needed in the following iterations, resulting in an overall better implementation. This CAD flow is challenging to work with because for a given FPGA researchers require access to each stage of the flow in an iterative fashion. This is particularly challenging when targeting modern commercial FPGAs, which are far more complex than a simple Lookup Table and Flip-Flop model generally used by the academic community. This dissertation describes a unified framework, called the Physical Synthesis Toolkit (PST), for research and development of optimizations for modern FPGA devices. PST provides access to modern FPGA devices and CAD tool flow to facilitate research. At the same time the amount of effort required to adapt the framework to a new FPGA device is kept to a minimum. To demonstrate that PST is an effective research platform, this dissertation describes optimization and modeling techniques that were implemented inside of it. The optimizations include: an area reduction technique for XOR-based logic circuits implemented on a 4-LUT based FPGA (25.3% area reduction), and a dynamic power reduction technique that reduces glitches in a circuit implemented on an Altera Stratix II FPGA (7% dynamic power reduction). The modeling technique is a novel toggle rate estimation approach based on the XOR-based decomposition, which reduces the estimate error by 37% as compared to the latest release of the Altera Quartus II CAD tool.

Leong Monk Ping. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (p. 255-278). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

by Xue-jie Zhang. / "December 1999." / Thesis (Ph.D.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (p. 144-[152]). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

Field Programmable Gate Array (FPGA) has a dominating market in digital system prototyping and reconfigurable computing. To make a flexible and efficient FPGA chip both the hardware architecture and the design tool should be further engineered. An innovative architecture always requires excellent development of EDA tools to fully explore the intrinsic merits of the hardware. / FPGA Technology Mapping is an important design automation problem which affects placement and routing dramatically. Depth-optimal technology mapping algorithms were proposed and produced quality mapping solution for delay minimization. However such algorithms have not yet considered to further reduce area consumption using the powerful logic transformation techniques. / On hardware side, we present a study on the effect of direct and fast routing hard-wires in FPGA routing architecture. Based on the routing pattern analyzed from real routing data, we proposed a so-called shortcut -based routing to handle short and localized routing requirements. Experimental results show that the shortcuts are well utilized and it allows a better average wirelength usage in the whole routing architecture. / On software side, we propose a versatile approach to combine logic transformation and technology mapping. In addition to a level-reduction scheme, we also present a method of reducing the number of LUTs used while keeping the depth optimality. Our approach is based on a greedy but effective heuristic to choose good alternative wires for transformation. Large number of experiments were conducted to analyze the effectiveness of the system. Our results show that our approach can effectively reduce at least 5% (up to 25%) of the area over initial mapping by various state-of-the-art FPGA technology mappers. Furthermore, we found that the delay performance can be improved by 5% when the area is reduced by our system. / Tang, Wai Chung. / Adviser: David Yu-Liang Wu. / Source: Dissertation Abstracts International, Volume: 70-06, Section: B, page: 3704. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2008. / Includes bibliographical references (leaves 70-74). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Abstracts in English and Chinese. / School code: 1307.

Cheung Yu Hoi Ocean. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 65-70). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims --- p.2 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Outline --- p.3 / Chapter 2 --- Virtual Private Network and FreeS/WAN --- p.4 / Chapter 2.1 --- Introduction --- p.4 / Chapter 2.2 --- Internet Protocol Security (IPSec) --- p.4 / Chapter 2.3 --- Secure Virtual Private Network --- p.6 / Chapter 2.4 --- LibDES --- p.9 / Chapter 2.5 --- FreeS/WAN --- p.9 / Chapter 2.6 --- Commercial VPN solutions --- p.9 / Chapter 2.7 --- Summary --- p.11 / Chapter 3 --- Cryptography and Field-Programmable Gate Arrays (FPGAs) --- p.12 / Chapter 3.1 --- Introduction --- p.12 / Chapter 3.2 --- The Data Encryption Standard Algorithm (DES) --- p.12 / Chapter 3.2.1 --- The Triple-DES Algorithm (3DES) --- p.14 / Chapter 3.2.2 --- Previous work on DES and Triple-DES --- p.16 / Chapter 3.3 --- The IDEA Algorithm --- p.17 / Chapter 3.3.1 --- Multiplication Modulo 2n + 1 --- p.20 / Chapter 3.3.2 --- Previous work on IDEA --- p.21 / Chapter 3.4 --- Block Cipher Modes of operation --- p.23 / Chapter 3.4.1 --- Electronic Code Book (ECB) mode --- p.23 / Chapter 3.4.2 --- Cipher-block Chaining (CBC) mode --- p.25 / Chapter 3.5 --- Field-Programmable Gate Arrays --- p.27 / Chapter 3.5.1 --- Xilinx Virtex-E´ёØ FPGA --- p.27 / Chapter 3.6 --- Pilchard --- p.30 / Chapter 3.6.1 --- Memory Cache Control Mode --- p.31 / Chapter 3.7 --- Electronic Design Automation Tools --- p.32 / Chapter 3.8 --- Summary --- p.33 / Chapter 4 --- Implementation / Chapter 4.1 --- Introduction --- p.36 / Chapter 4.1.1 --- Hardware Platform --- p.36 / Chapter 4.1.2 --- Reconfigurable Hardware Computing Environment --- p.36 / Chapter 4.1.3 --- Pilchard Software --- p.38 / Chapter 4.2 --- DES in ECB mode --- p.39 / Chapter 4.2.1 --- Hardware --- p.39 / Chapter 4.2.2 --- Software Interface --- p.40 / Chapter 4.3 --- DES in CBC mode --- p.42 / Chapter 4.3.1 --- Hardware --- p.42 / Chapter 4.3.2 --- Software Interface --- p.42 / Chapter 4.4 --- Triple-DES in CBC mode --- p.45 / Chapter 4.4.1 --- Hardware --- p.45 / Chapter 4.4.2 --- Software Interface --- p.45 / Chapter 4.5 --- IDEA in ECB mode --- p.48 / Chapter 4.5.1 --- Multiplication Modulo 216 + 1 --- p.48 / Chapter 4.5.2 --- Hardware --- p.48 / Chapter 4.5.3 --- Software Interface --- p.50 / Chapter 4.6 --- Triple-DES accelerator in LibDES --- p.51 / Chapter 4.7 --- Triple-DES accelerator in FreeS/WAN --- p.52 / Chapter 4.8 --- IDEA accelerator in FreeS/WAN --- p.53 / Chapter 4.9 --- Summary --- p.54 / Chapter 5 --- Results --- p.55 / Chapter 5.1 --- Introduction --- p.55 / Chapter 5.2 --- Benchmarking environment --- p.55 / Chapter 5.3 --- Performance of Triple-DES and IDEA accelerator --- p.56 / Chapter 5.3.1 --- Performance of Triple-DES core --- p.55 / Chapter 5.3.2 --- Performance of IDEA core --- p.58 / Chapter 5.4 --- Benchmark of FreeSAVAN --- p.59 / Chapter 5.4.1 --- Triple-DES --- p.59 / Chapter 5.4.2 --- IDEA --- p.60 / Chapter 5.5 --- Summary --- p.61 / Chapter 6 --- Conclusion --- p.62 / Chapter 6.1 --- Future development --- p.63 / Bibliography --- p.65

by Pan Jiao Feng. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1998. / Includes bibliographical references (leaves 89-93). / Abstract also in Chinese. / Abstract --- p.i / Acknowledgments --- p.v / List of Tables --- p.x / List of Figures --- p.xi / Chapter Chapter 1. --- Introduction --- p.1 / Chapter 1.1 --- Graph definitions --- p.2 / Chapter 1.2 --- The S box graph --- p.2 / Chapter 1.3 --- The file transfer graph --- p.4 / Chapter 1.4 --- "(g, f)-factor and (g, f)-factorization" --- p.5 / Chapter 1.5 --- Thesis contributions --- p.6 / Chapter 1.6 --- Organization of the thesis --- p.7 / Chapter Chapter 2. --- On the Optimal Four-way Switch Box Routing Structures of FPGA Greedy Routing Architectures --- p.8 / Chapter 2.1 --- Introduction --- p.9 / Chapter 2.1.1 --- FPGA model and S box model --- p.9 / Chapter 2.1.2 --- FPGA routing --- p.10 / Chapter 2.1.3 --- Problem formulation --- p.10 / Chapter 2.2 --- Definitions and terminology --- p.12 / Chapter 2.2.1 --- General terminology --- p.12 / Chapter 2.2.2 --- Graph definitions --- p.15 / Chapter 2.2.3 --- The S box graph --- p.15 / Chapter 2.3 --- Properties of the S box graph and side-to-side graphs --- p.16 / Chapter 2.3.1 --- On the properties of the S box graph --- p.16 / Chapter 2.3.2 --- The properties of side-to-side graphs --- p.19 / Chapter 2.4 --- Conversion of the four-way FPGA routing problem --- p.23 / Chapter 2.4.1 --- Conversion of the S box model --- p.24 / Chapter 2.4.2 --- Conversion of the DAAA model --- p.26 / Chapter 2.4.3 --- Conversion of the DADA model --- p.27 / Chapter 2.4.4 --- Conversion of the DDDA model --- p.28 / Chapter 2.5 --- Low bounds of routing switches --- p.28 / Chapter 2.5.1 --- The lower bound of the DAAA model --- p.29 / Chapter 2.5.2 --- The lower bound of the DADA model --- p.30 / Chapter 2.5.3 --- The lower bound of the DDDA model --- p.31 / Chapter 2.6 --- Optimal structure of one-side predetermined four-way FPGA routing --- p.32 / Chapter 2.7 --- Optimal structures of two-side and three-side predetermined four-way FPGA routing --- p.45 / Chapter 2.7.1 --- Optimal structure of two-side predetermined four-way FPGA routing --- p.46 / Chapter 2.7.2 --- Optimal structure of three-side predetermined four-way FPGA routing --- p.47 / Chapter 2.8 --- Conclusion --- p.49 / Appendix --- p.50 / Chapter Chapter 3. --- "Application of (0, f)-Factorization on the Scheduling of File Transfers" --- p.53 / Chapter 3.1 --- Introduction --- p.53 / Chapter 3.1.1 --- "(0,f)-factorization" --- p.54 / Chapter 3.1.2 --- File transfer model and its graph --- p.54 / Chapter 3.1.3 --- Previous results --- p.56 / Chapter 3.1.4 --- Our results and outline of the chapter --- p.56 / Chapter 3.2 --- NP-completeness --- p.57 / Chapter 3.3 --- Some lemmas --- p.58 / Chapter 3.4 --- Bounds of file transfer graphs --- p.59 / Chapter 3.5 --- Comparison --- p.62 / Chapter 3.6 --- Conclusion --- p.68 / Chapter Chapter 4. --- "Decomposition Graphs into (g,f)-Factors" --- p.69 / Chapter 4.1 --- Introduction --- p.69 / Chapter 4.1.1 --- "(g,f)-factors and (g,f)-factorizations" --- p.69 / Chapter 4.1.2 --- Previous work --- p.70 / Chapter 4.1.3 --- Our results --- p.72 / Chapter 4.2 --- Proof of Theorem 2 --- p.73 / Chapter 4.3 --- Proof of Theorem 3 --- p.79 / Chapter 4.4 --- Proof of Theorem 4 --- p.80 / Chapter 4.5 --- Related previous results --- p.82 / Chapter 4.6 --- Conclusion --- p.84 / Chapter Chapter 5. --- Conclusion --- p.85 / Chapter 5.1 --- About graph-based approaches --- p.85 / Chapter 5.2 --- FPGA routing --- p.87 / Chapter 5.3 --- The scheduling of file transfer --- p.88 / Bibliography --- p.89 / Vita --- p.94

Elliptic curve cryptosystems offer security comparable to that of traditional asymmetric cryptosystems, such as those based on the RSA encryption and digital signature algorithms, with smaller keys and computationally more efficient algorithms. The ability to use smaller keys and computationally more efficient algorithms than traditional asymmetric cryptographic algorithms are two of the main reasons why elliptic curve cryptography has become popular. As the popularity of elliptic curve cryptography increases, the need for efficient hardware solutions that accelerate the computation of elliptic curve point multiplications also increases. This dissertation introduces elliptic curve processor architectures suitable for the computation of point multiplications for curves defined over fields GF(2^m) and curves defined over fields GF(p). Each of the processor architectures presented here allows designers to tailor the performance and hardware requirements according to their performance and cost goals. Moreover, these architectures are well suited for implementation in modern field programmable gate arrays (FPGAs). This point was proved with prototyped implementations. The fastest prototyped GF(2^m) processor can compute an arbitrary point multiplication for curves defined over fields GF(2^167) in 0.21 milliseconds and the prototyped processor for the field GF(2^192-2^64-1) is capable of computing a point multiplication in about 3.6 milliseconds. The most critical component of an elliptic curve processor is its arithmetic unit. A typical arithmetic unit includes an adder/subtractor, a multiplier, and possibly a squarer. Some of the architectures presented in this work are based on multiplier and squarer architectures developed as part of the work presented in this dissertation. The GF(2^m) least significant bit super-serial multiplier architecture, the GF(2^m) most significant bit super-serial multiplier architecture, and a new GF(p) Montgomery multiplier architecture were developed as part of this work together with a new squaring architecture for GF(2^m).

Thesis (Master of Engineering in Electrical Engineering)--Cape Peninsula University of Technology, 2017. / The concept of forward error correction (FEC) coding introduced the capability of achieving near Shannon limit digital transmission with bit error rates (BER) approaching 10-9 for signal to noise power (Eb/No) values as low as 0.7. This brought about the ability to transmit large amounts of data at fast rates on bad/noisy communication channels. In nano-satellites, however, the constraints on power that limit the energy that can be allocated for data transmission result in significantly reduced communication system performance. One of the effects of these constraints is the limitation on the type of channel coding technique that can be implemented in these communication systems. Another limiting factor on nano-satellite communication systems is the limited space available due to the compact nature of these satellites, where numerous complex systems are tightly packed into a space as small as 10x10x10cm. With the miniaturisation of Integrated-Circuit (IC) technology and the affordability of Field-Programmable-Gate-Arrays (FPGAs) with reduced power consumption, complex circuits can now be implemented within small form factors and at low cost. This thesis describes the design, implementation and cost evaluation of a ½-rate convolutional encoder and the corresponding Viterbi decoder on an FPGA for nano-satellites applications. The code for the FPGA implementation is described in VHDL and implemented on devices from the Artix7 (Xilinx), Cyclone V (Intel-fpga), and Igloo2 (Microsemi) families. The implemented channel code has a coding gain of ~3dB at a BER of 10-3. It can be noted that the implementation of the encoder is quite straightforward and that the main challenge is in the implementation of the decoder.

Thesis (M.Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003. / Includes bibliographical references (leaves 99-100). / This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. / This thesis investigates the feasibility of utilizing a run-time partially reconfigurable FPGA to implement a sequence of high-speed digital signal processing filters. Rather than reconfiguring the entire device to modify part of a configuration, a modular architecture is designed to allow smaller segments of the device to be individually reconfigured while the remainder of the device continues to operate. This document describes the design, implementation, simulation, and benchmarking of a five-socket modular DSP architecture and compares the results to the performance of alternative digital signal processing methods, particularly that of software DSP subroutines run on a PowerPC processor. The result is a highly flexible architecture that supports the use of timing verified hardware subroutines that could be partially reconfigured onto the FPGA within 3ms. The highly parallel processing power of the FPGA design yields a performance of 5.825 billion multiply and accumulate operations per second while simulated running at 72.8MHz, more than 76 times faster than similar calculations measured on a MPC7410 processor. / by Justin D. McBride. / M.Eng.and S.B.

Tang Wai Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2005. / Includes bibliographical references (leaves 40-41). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Rewiring Algorithms --- p.3 / Chapter 2.1 --- REWIRE --- p.5 / Chapter 2.2 --- RAMFIRE --- p.7 / Chapter 2.3 --- GBAW --- p.8 / Chapter 3 --- FPGA Technology Mapping --- p.11 / Chapter 3.1 --- Problem Definition --- p.13 / Chapter 3.2 --- Network-flow-based Algorithms for FPGA Technology Mapping --- p.16 / Chapter 3.2.1 --- FlowMap --- p.16 / Chapter 3.2.2 --- FlowSYN --- p.21 / Chapter 3.2.3 --- CutMap --- p.22 / Chapter 4 --- LUT Minimization by Rewiring --- p.24 / Chapter 4.1 --- Greedy Decision Heuristic for LUT Minimization --- p.27 / Chapter 4.2 --- Experimental Result --- p.28 / Chapter 5 --- Conclusion --- p.38 / Bibliography --- p.40