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A Custom Computing Machine Solution for Simulation of Discretized Domain Physical SystemsPaar, Kevin J. 05 June 1996 (has links)
This thesis describes the implementation of a two-dimensional heat transfer simulation system using a Splash-2 Custom Computing Machine (CCM). This application was implemented as a proof of concept for utilizing CCMs in the simulation of physical systems. This paper discusses physical systems simulation and the need for discretizing the domain of such systems, along with the techniques used for mathematical simulation. Also discussed is the nature of CCMs, and why they are well suited to this application. A detailed description of the approach and implementation is included to full document the design, along with an analysis of the performance of the resulting system. / Master of Science
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Framework for Hardware Agility on FPGAsBhardwaj, Prabhaav 21 January 2011 (has links)
As hardware applications become increasingly complex, the supporting technology needs to evolve and adapt to the demands. Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit, General Purpose Processor, and System on Chip are the preferred devices for solving computational problems. Each of these platforms has its own specific advantages and disadvantages, which need to be accounted for during application development. Flexible radio communications has been dominated by Software Defined Radios. However, research in industry and universities has successfully developed run-time reconfiguration tools to make FPGA designs more flexible and thus vastly reducing configuration times. Developers now have a more powerful platform with dense Digital Signal Processor resources and the flexibility of SDR. Xilinx offers tools such as partial reconfiguration, which is a special modification of the standard tool-flow that supports configuration of the selected partial regions on an FPGA. The AgileHW project improves on the Xilinx tools resource allocation and routing scheme to increase the design agility and productivity. This thesis advances the AgileHW reconfigurable platform so developers can use the newer technology to build enhanced designs. / Master of Science
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Design and Implementation of an FPGA-based Adaptive filter Single-User ReceiverAtiniramit, Prinya 13 October 1999 (has links)
During the last decade, the wireless communications industry has grown rapidly. Driven by market demand, service providers are continuously looking for better systems. The main focus of continued research has been to increase the quality of services and system capacity. The Code Division Multiple Access (CDMA) cellular system had been proposed for use as a new standard for cellular telephone systems.
A great deal of research has been conducted to develop receiver structures useful for CDMA systems. Traditional receivers such as the correlation and RAKE receivers are vulnerable to the near-far problem, i.e., the problem encountered when one received signal power is stronger than another. This problem is common in mobile environments.
For single-user receivers, adaptive filtering techniques can be employed to alleviate multiple access interference and the near-far problem. In this thesis, an adaptive filter receiver is implemented on the FPGA-based configurable computing platform called GigaOps G900. By using FPGAs, designers can implement special-purpose signal processing architectures using specialized data paths, optimized sequencing, and pipelining while still providing some flexibility. This results in better overall system performance, resource utilization, and reduced power consumption. / Master of Science
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Implementing an Application Programming Interface for Distributed Adaptive Computing SystemsYao, Kuan 12 June 2000 (has links)
Developing applications for distributed adaptive computing systems (ACS) requires developers to have knowledge of both parallel computing and configurable computing. Furthermore, portability and scalability are required for developers to use innovative ACS research directly in deployed systems. This thesis presents an Application Programming Interface (API) implementation developed in a scalable parallel ACS system. The API gives the developer the ability to easily control both single board and multi-board systems in a network cluster environment. The API implementation is highly portable and scalable, allowing ACS researchers to easily move from a research system to a deployed system. The thesis details the design and implementation of the API, as well as analyzes its performance. / Master of Science
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A Cross Platform Method for FPGA Integrity CheckingBenz, Matthew Aaron 16 October 2007 (has links)
As embedded systems continue to evolve and the number of applications they support continues to increase, so does the diversity of the hardware they employ. As a result, the Field Programmable Gate Arrays (FPGAs), which have become fundamental elements in their design, have advanced in size and complexity as well. Because of this, it is now impossible to ignore the security implications that accompany such a progression. It is then not only important to prevent malicious attacks targeted at FPGAs from extracting the intellectual property contained in their configuration, but to now extend the research in this field by providing a cross-platform solution capable of securing the integrity of FPGA configurations at run-time. Today, there exist myriad attack strategies employed against FPGAs, the majority of which are seen in the form of semi-invasive attacks. These attacks manipulate the configuration of an FPGA and typically modify the state of the transistors that make up said configuration.
This thesis introduces a multi-platform method for checking the integrity of an FPGA's configuration. The details of the system's design and implementation are discussed in addition to the analysis of the design trade-offs met when employing the system across multiple FPGA families. The system is implemented entirely in hardware and resides on-chip, providing an FPGA the ability to act as private entity capable of successfully detecting when it has been maliciously attacked. / Master of Science
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Design of a controller for an FPGA-based reconfigurable computing architectureJamkhandi, Piyush S. 01 April 2000 (has links)
No description available.
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FPGA prototyping of custom GPGPUsNigania, Nimit 08 January 2014 (has links)
Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping of general-purpose graphics processing units (GPGPUs) on field programmable gate arrays (FPGAs) using a novel tool chain. This hardware flow combined with the higher level simulation flow using the same source code allowed us to create a whole tool chain to study and build future architectures using new technologies. It also gave us enough flexibility at different granularities to make architectural decisions. We will also discuss some example systems that were built using this tool chain along with some results.
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Modular Field Programmable Gate Array Implementation of a MIMO TransmitterShekhar, Richa 10 1900 (has links)
ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / Multiple-Input Multiple-Output (MIMO) systems have at least two transmitting antennas, each generating unique signals. However some applications may require three, four, or more transmitting devices to achieve the desired system performance. This paper describes the design of a scalable MIMO transmitter, based on field programmable gate array (FPGA) technology. Each module contains a FPGA, and associated digital-to-analog converters, I/Q modulators, and RF amplifiers needed to power one of the MIMO transmitters. The system was designed to handle up to a 10 Mbps data rate, and transmit signals in the unlicensed 2.4 GHz ISM band.
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The design and testing of a superconducting programmable gate arrayVan Heerden, Hein 03 1900 (has links)
Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2006. / This thesis investigates to the design, analysis and testing of a Superconducting Programmable
Gate Array (SPGA). The objective was to apply existing programmable logic concepts to
RSFQ circuits and in the process develop a working prototype of a superconducting programmable
logic device. Various programmable logic technologies and architectures were
examined and compared to find the best solution. Using Rapid Single Flux Quantum (RSFQ)
circuits as building blocks, a complete functional design was assembled incorporating a routing
architecture and logic blocks. The Large-Scale Integrated circuit (LSI) layout of the final
chip is presented and discussed followed by a discussion on testing. This thesis demonstrates
the successful implementation of a fully functional reprogrammable logic device using
RSFQ circuitry.
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Radiation tolerant implementation of a soft-core processor for space applicationsVan der Horst, Johannes Gerhardus 03 1900 (has links)
Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2007. / The availability of high density FPGAs has made the use of soft-core processors an attractive
proposition for the low volume space market. Soft-core processors combine
the power of programmable logic with the ease of use of a conventional processor to
provide a highly customisable solution. However, the SRAM FPGAs used as implementation
platform are especially susceptable to radiation induced single event upsets,
due to the sensitivity of their configuration memory. To safely use these processors in
a space environment requires the modification of the processor to safely mitigate these
effects.
This thesis presents the process followed to develop and test a fault tolerant implementation
of an 8-bit PicoBlaze soft-core processor on a Xilinx Spartan-3 SRAM FPGA.
A thorough investigation was made into the available methods that can be used to
mitigate single event upsets, in order to identify the most suitable ones. Guidelines
for the application of SEU mitigation techniques to SRAM FPGAs were proposed. A
single event upset simulator was designed and constructed to compare the different
techniques. It mimics SEUs by injecting errors into the configuration memory of an
FPGA.
The results of error injection were used to develop a PicoBlaze implementation with
limited overhead, while it still offers a high degree of error mitigation.
Three different designs were tested by proton irradiation to verify the protection afforded
by the mitigation techniques. It was found that protected designs were more
robust. The cross-section of the FPGA was also determined, which can be used with
the SEU simulator to predict the dynamic cross-section of designs.
The work contained in this thesis demonstrates the use of open-source intellectual
property with commercial-off-the-shelf components to develop a robust component for
use in the miniature spacecraft market.
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