Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (leaves 37-40).

Thesis (M.S.)--Florida State University, 2004. / Advisor: Dr. Uwe Meyer-Baese, Florida State University, College of Engineering, Dept. of Electrical and Computer Engineering. Title and description from dissertation home page (viewed Sept. 15, 2005). Document formatted into pages; contains ix, 108 pages. Includes bibliographical references.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2005. / Includes bibliographical references (p. 81-86).

Thesis (M.S.)--Tennessee Technological University, 2009. / Title from title page screen (viewed on June 25, 2010). Bibliography: leaves 93-96.

Thesis (M.S.)--Oregon State University, 2007. / Printout. Includes bibliographical references (leaves 73-76). Also available on the World Wide Web.

The area of fault-handling in reconfigurable logic devices is one that continues to receive research attention in the field of engineering. Field Programmable Gate Arrays (FPGAs) are reconfigurable logic devices that have become an essential element in electronic hardware used for space applications, for instance deep space satellites. When electronic devices such as FPGAs are launched into space, they are relentlessly exposed to fault-inducing hazards such as high levels of radiation and extreme temperatures. The ability of the device to maintain and correct its functionality while experiencing these harsh conditions is vital to a successful mission by today's technological standards. Many techniques have been proposed for the purpose of detecting and repairing hardware faults that occur in reconfigurable logic devices. The implementation of a Genetic Algorithm (GA) as the means of repairing a faulty component has become a popular method among such techniques. A great deal of success has been demonstrated by the use of GAs in fault-repair, but there is room for improvement in the completeness of a given repair. This thesis addresses this issue by exploring the possible outcomes of implementing a voting system to work in parallel with a particular GA. Throughout the first two chapters, a general overview ofFPGAs and faulthandling techniques is provided. The advantages and disadvantages of each technique are mentioned to help re-emphasize the main purpose for the research being conducted. Once a solid background has been established regarding the main ideas behind this work, the thesis presents an in-depth description of the problem and the experimental approach that is taken. The work involves experiments which are run using a simulated FPGA that is coded in C++. A genetic algorithm is included in the program in order to simulate the repair process. By varying the parameters of the GA, as well as experimenting with the addition of a voting scheme to enhance the performance, meaningful results are discovered and presented. Fault-handling techniques proposed in the future will have a better idea of whether or not it would be beneficial to include a voting scheme to improve success.

No description available.

This thesis addresses the partitioning problem for configurable computing machines. Specifically, this thesis presents algorithms to partition chain-structured task graphs across configurable computing machines. The algorithms give optimal solutions for throughput and total execution time for these problems under constraints on area, pin count, and power consumption. The algorithms provide flexibility for applying these constraints while remaining polynomial in complexity. Proofs of correctness as well as an analysis of runtime complexity are given. Experiments are performed to illustrate the runtime of these algorithms. / Master of Science

FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool suite. Several aspects of the design process are discussed, including implementation, simulation, debugging, and hardware interfacing to a reconfigurable computing platform. The DWT lends itself to a straightforward implementation in hardware, requiring relatively simple logic for control and address generation circuitry. Through the application of RTR techniques to the DWT, this research attempts to exploit certain advantages that are unobtainable with static implementations. Performance results of the DWT core are presented, including speed of operation, resource consumption, and reconfiguration overhead times. / Master of Science

The proposed demodulator is an all-digital implementation of a FM demodulator. The proposed design intends to implement a FM demodulator for high-speed applications, which makes the requirements for analog components minimal. The proposed circuit is an all-digital quadrature demodulator, where the individual components have been implemented without using any multipliers. The topology uses a Pulse width modulation (PWM) block to avoid the need for a DAC. The Xilinx virtex-7 FPGA has been used as the reference device for the work. The circuit is validated through behavioral simulations and the results conclude the proposed circuit demodulates the targeted FM channel and provides the spectrum information for the targeted FM channel / Master of Science / With the rise in popularity of reconfigurable hardware, such as FPGAs, digital signal processing has become one of the most widespread usage of such devices. The major advantage of using FPGAs for implementing signal processing algorithms is that they provide very less time to market and can be re-modeled or modified in easily. Moreover, the netlists designed for FPGAs can be easily translated to ASICs. As wireless communication has become omnipresent, modulation and demodulation schemes have become an area of great interest. With the increase in data rates for the modern-day communication systems, the digital implementation of these algorithms is becoming more and more common. This is further aided by the advancements in high-speed ADCs and the Electronic Design Automation (EDA) tools, which have made the usage of FPGAs lot more feasible and a lot more efficient. This work discusses the demodulation scheme for one of the most widespread modulation algorithms, Frequency Modulation (FM). An all-digital FM demodulator design is proposed for highspeed implementation on FPGAs. The proposed design is an all-digital quadrature I-Q based demodulator.