Line current distortion is an important issue to a high-power current source rectifier(CSR) system. There are two main challenges related to this issue. First, the CSR input LC resonance can be affected by the variation of the source inductance from the power system and the effects of the CSR DC side circuit, which may lead to a line current distortion higher than expected. Another challenge is that the traditional high-power CSR using Selective Harmonic Elimination (SHE) pulse-width modulation (PWM) technique attempts to eliminate certain harmonics in the PWM current, which limits its ability for line current harmonic control. To control the CSR line current harmonics, this thesis focuses on two aspects: 1) the analysis and design of CSR input filter to avoid unexpected input LC resonance, and 2) the development of a new PWM scheme that can compensate the effects of the grid voltage harmonics and DC link current ripples. The thesis work has been validated by simulations and on an experimental CSR prototype. / Power Engineering and Power Electronics

Saab Aerosystems, a part of Saab AB, has the overall responsibility for the development of the fourth generation fighter aircraft JAS 39 Gripen. When planning a mission for one or more aircrafts, a computer program called Mission Support System is used. Some of the data from the planning is then transferred to the actual aircraft. Today there are some unwanted restrictions in the planning software. One of these restrictions is about the fact that a number of parameters that controls the output from a planned mission are not configurable runtime, i.e. a reinstallation at customers location is needed to change this. The main purpose of this thesis was to propose a new design and a new framework that solves the inflexibility described above. The design should also be validated by a test implementation. A number of different designs were proposed and four of these were selected to be candidates for being implemented. An important tool used when developing the designs was the theory of design patterns. To choose one of the four a ranking system, based on both measurable metrics and non-measurable experience, was used. One design was selected to be the best and after implementing of the design it was considered to be valid. Future work can consist of rewriting all modules in the software to use the new framework.

Graph signal processing analyzes signals supported on the nodes of a network with respect to a shift operator matrix that conforms to the graph structure. For shift-invariant graph filters, which are polynomial functions of the shift matrix, the filter response is defined by the value of the filter polynomial at the shift matrix eigenvalues. Thus, information regarding the spectral decomposition of the shift matrix plays an important role in filter design. However, under stochastic conditions leading to uncertain network structure, the eigenvalues of the shift matrix become random, complicating the filter design task. In such case, empirical distribution functions built from the random matrix eigenvalues may exhibit deterministic limiting behavior that can be exploited for problems on large-scale random networks. Acceleration filters for distributed average consensus dynamics on random networks provide the application covered in this thesis work. The thesis discusses methods from random matrix theory appropriate for analyzing adjacency matrix spectral asymptotics for both directed and undirected random networks, introducing relevant theorems. Network distribution properties that allow computational simplification of these methods are developed, and the methods are applied to important classes of random network distributions. Subsequently, the thesis presents the main contributions, which consist of optimization problems for consensus acceleration filters based on the obtained asymptotic spectral density information. The presented methods cover several cases for the random network distribution, including both undirected and directed networks as well as both constant and switching random networks. These methods also cover two related optimization objectives, asymptotic convergence rate and graph total variation.

With the advent of wide bandgap (WBG) semiconductor devices, the electromagnetic interference (EMI) emissions are more pronounced due to high slew rates in the form of high dv/dt and high di/dt at higher switching frequencies compared to the traditional silicon technology. To comply with the stringent conducted emission requirements, EMI filters are adopted to attenuate the high frequency common mode (CM) and differential mode (DM) noise through the propagation path. However, self and mutual parasitic components are known to degrade the EMI filter performance. While parasitic cancellation techniques have been discussed at length in prior literature, most of them have focused mainly on single phase applications. As such this work focuses on extending the preexisting concepts to three-phase systems. Novel component placement, winding strategy as well as shielding and grounding techniques were developed to desensitize the influence of the parasitic effects on a three-phase multi-stage filter. The effectiveness of the three-phase filter structure employing the proposed methodologies has been validated via noise measurements at the line impedance stabilization network (LISN) in a 15kW rated motor drive system. Consequently, general design guidelines have been formulated for filter topologies with different inductor and capacitor form-factors. / Master of Science / The adoption of wide bandgap (WBG) semiconductor devices, such as Silicon Carbide (SiC) or Gallium Nitride (GaN) transistors, improves the power density with higher slew rates and switching frequencies compared to the traditional Silicon technology. However, the high switching speeds and high frequencies have generated higher electromagnetic interference (EMI) noise in the surroundings. To comply with the conducted emission requirements at the grid terminal, EMI filter is mandatory to attenuate the high frequency EMI noise that flows into grid. However, near field and the effect of parasitic components are known to degrade the filter performance at the higher end of frequency spectrum where the limit lines are typically stringent. While parasitic cancellation techniques have been discussed at length in prior literature, most of them has focused mainly on single phase applications. Therefore, this thesis aims to extend the pre-existing concepts to compensate the mutual and self-parasitic coupling components in a three-phase multi-stage filter. In this regard, novel component placement, winding strategy as well as shielding and grounding techniques were developed to compensate for the parasitic effects in a three- phase multi-stage filter. The effectiveness of the three-phase filter structure employing the proposed methodologies has been validated in a 15kW rated motor drive system. Consequently, general design guidelines have been formulated for filter design with minimal parasitic effects.

No description available.

<p> The modeling, design and simulation of optical waveguides and integrated optical triplexer filters are presented. The work includes two subjects. One is application of improved three-point fourth-order finite-difference method and the other is design of triplexer optical filter for fiber-to-the-home passive optical network.</p> <p> The improved three-point fourth-order finite-difference method utilizes special format of one dimensional Helmholtz Equation and adopts generalized Douglas scheme and boundary conditions matching at interface. The modal analysis of dielectric slab waveguides and metal slab waveguides that support Surface Plasmon Plaritons by using this improved fourth-order finite-difference method is compared by using traditional first-order central difference method. The application of using improved three-point fourth-order finite-difference method in modal analysis of optical fiber waveguide is also provided.</p> <p> The modeling, design and simulation of monolithically integrated triplexer optical filter based on silicon wire waveguide are presented in detail. The design of this device facilitates multi-mode interference device (MMI) and arrayed waveguide grating (AWG) device to function as coarse wavelength division multiplexing and dense wavelength division multiplexing respectively. The MMI is used to separate downstream signs for upstream signal and AWG is used to further separate two down-stream signals with different bandwidths required. This design is validated by simulation that shows excellent performance in terms of spectral response as well as insertion loss.</p> / Thesis / Master of Applied Science (MASc)

Rapidly-increasing medium-voltage power electronics applications in emerging industry systems, including electrical ships, more electric aircraft, and microgrids, have emphasized the critical need for highly energy-efficient, reliable, and fast switching devices. As a result, Wide-Bandgap (WBG) devices have gained considerable interest over conventional silicon-based switches in recent years. For example, emerging WBG devices have unlocked new dimensions for modern motor drive systems with increased efficiency, switching frequency, and superior power density. Commercially-developed WBG devices such as Silicon Carbide (SiC) and Gallium Nitride (GaN) offer promising opportunities to meet those pressing requirements. However, the fast switching operation of WBG devices may cause substantially increased EMI emissions in medium-voltage applications, which can decrease the overall system’s performance or merits of power converters. This will be particularly an issue in a system where electric ground is unavailable, such as an electric ship, as a large Electro-Magnetic Interference current will be circulating within the system. The EMI in the WBG switch module will be emitted up to 500 MHz. This is the near radio-frequency (RF) band whose impact had not been clearly understood or properly analyzed in the power electronics field until recently. With new and critical challenges in recent years, to reliably adopt WBG devices in emerging power systems, there has been significant effort to improve electromagnetic compatibility (EMC) with new EMI mitigation techniques that comply with existing standards, including International Special Committee on Radio Interference (CISPR), Federal Communications Commission (FCC), Department of Defense (DOD), International Electro-Technical Commission (IEC), etc. This research investigates the common-mode EMI in networked power electronics-enabled power systems. Common-mode EMI phase information is a vital degree of freedom in EMI study that has not been considered in the state of the art. The EMI phase information reduces EMI without implementing any active or passive filter circuit. An effective and less complex method is introduced to reduce EMI in power electronics network. The work includes developing hybrid filter with passive and virtual filter. Including virtual filter reduces the passive common mode choke weight and volume significantly. Finally, a simplified switching node capacitance characterization technique for packaged WBG SiC has been introduced.

Power factor correction (PFC) converter is a species of switching mode power supply (SMPS) which is widely used in offline frond-end converter for the distributed power systems to reduce the grid harmonic distortion. With the fast development of information technology and multi-media systems, high frequency PFC power supplies for servers, desktops, laptops and flat-panel TVs, etc. are required for more efficient power delivery within limited spaces. Therefore the critical conduction mode (CRM) PFC converter has been becoming more and more popular for these information technology applications due to its advantages in inherent zero-voltage soft switching (ZVS) and negligible diode reverse recovery. With the emerging of the high voltage GaN devices, the goal of achieving soft switching for high frequency PFC converters is the top priority and the trend of adopting the CRM PFC converter is becoming clearer. However, there is the stringent electromagnetic interference (EMI) regulation worldwide. For the CRM PFC converter, there are several challenges on meeting the EMI standards. First, for the CRM PFC converter, the switching frequency is variable during the half line cycle and has very wide range dependent on the AC line RMS voltage and the load, which makes it unlike the traditional constant-frequency PFC converter and therefore the knowledge and experience of the EMI characteristics for the traditional constant-frequency PFC converter cannot be directly applied to the CRM PFC converter. Second, for the CRM PFC converter, the switching frequency is also dependent on the inductance of the boost inductor. It means the EMI spectrum of the CRM PFC converter is tightly related the boost inductor selection during the design of the PFC power stage. Therefore, unlike the traditional constant-frequency PFC converter, the selection of the boost inductor is also part of the EMI filter design process and EMI filter optimization should begin at the same time when the power stage design starts. Third, since the EMI filter optimization needs to begin before the proto-type of the CRM PFC converter is completed, the traditional EMI-measurement based EMI filter design will become much more complex and time-consuming if it is applied to the CRM PFC converter. Therefore, a new methodology must be developed to evaluate the EMI performance of the CRM PFC converter, help to simplify the process of the EMI filter design and achieve the EMI filter optimization. To overcome these challenges, a novel mathematical analysis method for variable frequency PFC converter is thus proposed in this dissertation. Based on the mathematical analysis, the quasi-peak EMI noise, which is specifically required in most EMI regulation standards, is investigated and accurately predicted for the first time. A complete approximate model is derived to predict the quasi-peak DM EMI noise for the CRM PFC converter. Experiments are carried out to verify the validity of the prediction. Based on the DM EMI noise prediction, worst case analysis is carried out and the worst DM EMI noise case for all the input line and load conditions can be found to avoid the overdesign of the EMI filter. Based on the discovered worst case, criteria to ease the DM EMI filter design procedure of the CRM boost PFC are given for different boost inductor selection. Optimized design procedure of the EMI filter for the front-end converter is then discussed. Experiments are carried out to verify the validity of the whole methodology. / Ph. D. / Power factor correction (PFC) converter is widely used in offline frond-end converter for the distributed power systems to reduce the grid harmonic distortion. With the fast development of information technology and multi-media systems, high frequency PFC power supplies for servers, desktops, laptops and flat-panel TVs, etc. are required for more efficient power delivery within limited spaces. Therefore the critical conduction mode (CRM) PFC converter has been becoming more and more popular for these information technology applications. However, there is the stringent electromagnetic interference (EMI) regulation worldwide. For the CRM PFC converter, there are many challenges on meeting the EMI standards. To overcome these challenges, a novel mathematical analysis method for variable frequency PFC converter is thus proposed in this dissertation. A complete approximate model is derived to predict the quasi-peak DM EMI noise for the CRM PFC converter. Experiments are carried out to verify the validity of the prediction. Based on the DM EMI noise prediction, worst case analysis is carried out and based on the discovered worst case, criteria to ease the DM EMI filter design procedure of the CRM boost PFC are given for different boost inductor selection. Optimized design procedure of the EMI filter for the front-end converter is then discussed. Experiments are carried out to verify the validity of the whole methodology.

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die.

Grid-connected inverters have wide application in the field of distributed generation and power quality. As the power level demanded by these applications increase, the design and performance evaluation of these converters become important. In the present work, a 50 kVA three-phase back-to-back connected inverter with output LCL filter is built to study design and performance evaluation aspects of grid-connected inverters. The first part of the work explores the split-capacitor resistive-inductive (SC-RL) passive damping scheme for the output LCL filter of a three-phase grid-connected inverter. The low losses in the SC-RL scheme makes it suitable for high power applications. The SCRL damped LCL filter is modelled using state space approach. Using this model, the power loss and damping are analysed. A method for component selection that minimizes the power loss in the damping resistors while keeping the system well damped is proposed. Analytical results show the losses to be in the range of 0.05-0.1% and the quality factor to be in the range of 2.0-2.5. These results are validated experimentally. In the second part of the work, a test method to evaluate the thermal performance of the semi-conductor devices of a three-phase grid-connected inverter is proposed. The method eliminates the need for high power sources, loads or any additional power converters for circulation of power. Only energy corresponding to the losses is consumed. The capability of the method to evaluate the thermal performance of the DC bus capacitors and the output filter components is also explored. The method can be used with different inverter configurations -three-wire or four-wire and for different PWM techniques. The method has been experimentally validated at a power level of 24kVA. In the third part of the work, the back-to-back connected inverter is programmed as a hardware grid simulator. The hardware grid simulator emulates the real-time grid and helps create grid disturbances often observed at the point of common coupling in an ac low voltage grid. A novel disturbance generation algorithm has been developed, analysed and implemented in digital controller using finite state machine model for control of the grid simulator. A wide range of disturbance conditions can be created using the developed algorithm. Experimental tests have been done on a linear purely resistive load, a non-linear diode-bridge load and a current-controlled inverter load to validate the programmed features of the grid simulator.