Thesis (Ph. D.)--University of Texas at Austin, 2000. / Vita. Includes bibliographical references (leaves 97-112). Available also in a digital version from Dissertation Abstracts.

Thesis (M. Sc.)--York University, 2001. Graduate Programme in Chemistry. / Typescript. Includes bibliographical references (leaves 85-90). Also available on the Internet. MODE OF ACCESS via web browser by entering the following URL: http://wwwlib.umi.com/cr/yorku/fullcit?pMQ71609.

As semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to meet the demands for high-density, low-cost, low-power, high-speed, better endurance and longer retention time. As traditional continuous floating gate flash struggles to balance the trade-off between high speed and retention requirement, nanocrystal (NC) floating gate flash has attracted more and more interest recently due to its advantages over traditional flash memories in many areas such as better device scaling, lower power consumption and improved charge retention. However, there are still two major challenges remaining for embedded NC synthesis: the deposition method and the size and distribution control. Nowadays using bio-nano techniques such as DNA, virus or protein for NC synthesis and assembly has become a hot topic and feasible for actual electronic device fabrication. In this dissertation a new method for NC deposition wherein a colloidal suspension of commercially-available NCs was organized using a self-assembled chaperonin array. The chaperonin array was applied as a scaffold to mediate NCs into an assembly with uniform spatial distribution on Si wafers. By using this method, we demonstrated that colloidal PbSe and Co NCs in suspension can self-assemble into ordered arrays with a high density of up to 10¹²cm⁻². MOSCAP and MOSFET memory devices were successfully fabricated with the chaperonin protein mediated NCs, showing promising memory functions such as a large charge storage capacity, long retention time and good endurance. The charge storage capacity with respect to material work function, NC size and density was explored. In addition to NC engineering, the tunnel barrier was engineered by replacing traditional SiO₂ by high-k material HfO₂, giving a higher write/erase speed with a reduced effective oxide thickness (EOT). Suggestions for future research in this direction are presented in the last part of this work. / text

Flash droughts refer to those droughts that intensify rapidly in spring and summer, coupled with a strong increase in summer extreme temperatures, such as those that occurred over Texas in 2011 and the Great Plains in 2012. Climate models failed to predict these flash droughts in 2011 and 2012 and are ambiguous in projecting their future changes, largely because of models’ weaknesses in predicting summer rainfall and soil moisture feedbacks. In contrast, climate models are more reliable in simulating changes of large‐scale circulation and temperatures during winter and spring seasons. Thus, we developed and tested a physical climate indicator of the risk of “flash” droughts in summer by using the large-scale circulation and land surface conditions in winter and spring based on observed relationships between these conditions and their underlying physical mechanisms established by previous observational studies and numerical model simulations. My master research focuses on the spatial distribution of this indicator globally to see how broadly it could be applied. We also compare the different factors to see which one is the dominant contributor to drought in different area. We find that the indicator performs well at capturing the development and termination of a drought. There is much opportunity to develop and improve the indicator further. / text

Mainstream non-volatile memory technology dominated by the planar Flash transistor with continuous floating-gate has been historically improved in density and performance primarily by means of process scaling, but is currently faced with significant hindrances to its future scaling due to fundamental constraints of electrostatics and reliability. This dissertation is based on exploring two pathways for circumventing scaling limitations of the state-of-the-art Flash memory technology. The first part of the dissertation is based on demonstrating a vertical Flash memory transistor with nanocrystal floating-gate, while the second part is based on developing fundamental understanding of the operation of Phase Change Memory. A vertical Flash transistor can allow the theoretical minimum cell area and a nanocrystal floating-gate on the sidewalls is shown to allow a thinner gate-stack further conducive to scaling while still providing good reliability. Subsequently, the application of a technique of protein-mediated assembly of preformed nanocrystals to the sidewalls of the vertical Flash transistor is also demonstrated and characterized. This technique of ordering pre-formed nanocrystals is beneficial towards achieving reproducible nanocrystal size uniformity and ordering especially in a highly scaled vertical Flash cell, rendering it more amenable to scaling and manufacturability. In both forms, the vertical Flash memory cell is shown to have good electrical characteristics and reliability for the viability of this cell design and implementation. In the remaining part of this dissertation, studies are undertaken towards developing fundamental understanding of the operational characteristics of Phase Change Memory (PCM) technology that is expected to replace floating-gate Flash technology based on its potential for scaling. First, a phenomenon of improving figures of merit of the PCM cell with operational cycles is electrically characterized. Based on the electrical characterization and published material characterization data, a physical model of an evolving "active region" of the cell is proposed to explain the improvement of the cell parameters with operational cycles. Then, basic understanding is developed on early and erratic retention failure in a statistically significant number of cells in a large array and, electrical characterization and physical modeling is used to explain the mechanism behind the early retention failure.

The quest for smaller and faster integrated circuits (ICs) continues, but traditional photolithography, the patterning process used to fabricate them, is rapidly approaching its physical limits. Step and Flash Imprint Lithography (S-FIL®) is a low-cost patterning technique which has shown great potential for next generation semiconductor manufacturing. To date, all methods of imprint lithography have utilized a sacrificial resist to produce device features. Our goal has been to develop functional materials such as insulators that can be directly patterned by S-FIL and then remain as a part of the end product. Directly patternable dielectric (DPD) materials must meet multiple mechanical and physical requirements for application in microelectronic devices. In some cases these requirements are conflicting, which leads to material design challenges. Many different materials and curing methods have been evaluated. Thiol-ene based approaches to patterning hyperbranched materials incorporating Polyhedral Oligomeric Silsesquioxanes (POSS) have shown the greatest promise. Thiol-ene polymerization takes place by a free radical mechanism, but it has the advantage over acrylates of not being inhibited by the presence of oxygen. This greatly eases some engineering design challenges for the S-FIL process. A number of thiol-ene formulations have been prepared and their mechanical and electrical properties evaluated. SFIL-R has been introduced as an alternative technology to SFIL. SFIL-R offers improvements to SFIL in several ways, but requires a high silicon content, low viscosity, planarizing material. Photopolymerizable branched siloxanes were synthesized and evaluated to function as a planarizing topcoat for this technology. Both SFIL and SFIL-R require a clean separation of the template from the resist material. Fouling of templates is a major concern in imprint lithography and fluorinated materials are used to treat templates to lower their surface energy for better separation. It has been observed that the template treatment degrades over time and needs to be replaced for further imprinting. A fluorinated silazane was designed to repair the degraded areas. This material was evaluated and functions as designed. / text

The continued speed improvement of serial links and appearance of new communication technologies, such as ultra wideband (UWB), have introduced increasing demands on the speed and power specifications of high speed low to medium resolution analog to digital converters (ADCs). While multi channel ADCs can achieve high speeds, they often require extensive and costly post fabrication calibration. A single channel 4 bit flash ADC, suitable for abovementioned or similar applications, implemented entirely using current mode logic (CML) blocks, is presented. CML implementation allows for high sampling rates, while typically providing low power consumption at high speeds. To improve the conversion rate, both the analog (comparator array) and the digital (encoder) parts of the ADC are fully pipelined. Furthermore, the logic functions in the encoder are reformulated to reduce wire crossings and delay and to equalize the wires lengths in the layout. To keep the design simple, inductors are avoided. As a result, a compact design with small wire parasitics is achieved. Moreover, some geometric layout techniques, including a common centroid layout for the resistor ladder, are introduced to reduce the effect of mismatches to eliminate the use of digital calibration. The ADC is designed and fabricated in 0.18um CMOS and operates at 4GS/s. It achieves an effective number of bits (ENOB) of 3.71 (3.14, 2.75) for a 10MHz (0.501GHz, 1.491GHz) signal sampled at 4GS/s (3GS/s, 3GS/s). Differential/integral nonlinearity (DNL/INL) errors are between +/-0.35LSB and +/-0.26LSB, respectively. The ADC consumes 43mW from a 1.8V supply and occupies 0.06mm2 active area. Due to the use of CML circuits, the ADC achieves the highest speed reported for a single channel 4 bit ADC in a 0.18um CMOS technology. It also reports the best power performance among the 4-bit ADCs with similar or higher speeds. The active area is also among the smallest reported. In addition, in this thesis, the signal to noise ratio (SNR) of an ADC is formulated in terms of its INL performance. The related formulas in the literature are not accurate for low resolution ADCs, and yet they do not take the input waveform into account. Two standard waveforms, ramp and sinusoid, are considered here. The SNR formulas are derived and confirmed by simulation results.

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