Flip Chip in Package (FCIP) has been developed to achieve the assembly process with area array interconnects. Particularly, a high I/O count coupled with finer pitch area array interconnects structured FCIP can be achieved using no-flow underfill assembly process. Using the assembly process, a high, stable yield assembly process recently reported with eutectic lead-tin solder interconnections, 150 µm pitch, and I/O counts in excess of 3000. The assembly process reported created a large number of voids among solder interconnects in FCIP. The voids formed among solder interconnections can propagate, grow, and produce defects such as solder joint cracking and solder bridging. Moreover, these voids can severely reduce reliability performance. Indeed, many studies were conducted to examine the void formation in FCIP. Based on the studies, flip chip geometric design, process conditions, and material formulation have been considered as the potential causes of void formation. However, the present research won't be able to identify the mechanism of void formation, causing a lot of voids in assembly process without consideration of chemical reaction in the assembly process with a fine-pitch, high I/O density FCIP. Therefore, this research will present process technology necessary to achieve high yields in FCIP assemblies using no-flow underfills and investigate the underlying problem of underfill void formation in these assemblies. The plausible causes of void formation will be investigated using experimental techniques. The techniques will identify the primary source of the void formation. Besides, theoretical models will be established to predict the number of voids and to explain the growth behavior of voids in the FCIP. The established theoretical models will be verified by experiments. These models will validate with respect to the relationship between process parameters to achieve a high yield and to minimize voids in FCIP assemblies using no-flow underfill materials regarding process as well as material stand points. Eventually, this research provides design guideline achieving a high, stable yield and void-free assembly process.

In recent years, even though the light output of GaN-based LED continues to increase, the brightness (~20 lm/W) is still low compared to conventional lighting systems and it is necessary to further improve the light extraction of LEDs. In this study, we utilize flip-chip technique, photoresist microlenses, reflectors and thermoelectric cooler to increase the light extraction of GaN MQW LED. Electroluminescence (EL) and power angular distribution are used to measure the light output intensity of LED. From temperature dependent current-voltage (I-V-T) characteristics, the charge carrier transport mechanisms at different biased regions are also investigated. In the results, back emission of LED with SiO2/Al reflector has maximum light intensity ( 3.28£gW ) , which is higher than front emission one ( 2.73£gW ) in vertical emitting area ( at 90 angles). LED with P.R. microlenses (refractive index, n=1.62) on backside could improve the light extraction of LED (about 1.2 times) as well. The enhancement of light output is duo to the reduction of light absorption from the metal contact and Fresnel¡¦s transmission losses at GaN (n=2.4)/air (n=1) interface. Finally, we fabricate a high brightness LED with above light enhancement design. EL intensity of LED is increased about 1.25 times than conventional one. Therefore, we can manufacture a LEDs array with above designs to obtain high light output for future solid-state illumination.

To calculate the characteristics of electronic parts is divided by 1.Chip. 2.Assembly, i.e. package. 3. PCB (Printed Circuit Board). Analizing the electrical characteristics of package needs consideration from all system can distinguish the influence of function. Although the analysis method may be change but we can get the characteristics results from the parameters of circuit element (i.e. Resistance, Inductance, Capacitance). Different measurement or modeling technology can prove that the list data is correct. That moisture in plastic packages can cause cracking or delamination during the surface mount assembly process. During this process, the packages are heated to 220-240¢J. At these temperatures, any moisture present in the plastic vaporizes and exerts stresses in the package, which can cause delamination between the mold compound and the leadframe or die. The mismatch in thermal expansion coefficients of the package¡¦s components also induces stresses. If these combined stresses are greater than the fracture strength of the plastic, cracks will form. The susceptibility of a package to cracking depends on: 1.amount of absorbed moisture, 2.die size, 3.package design, 4.mold compound characteristics, 5.solder reflow temperature profile. Widely, flip chip technology is defined as mounting the chip to a substrate with any kind of materials and methods, as long as the chip surface (active area) is facing to the substrate. The advantages of FC-BGA is¡G1.Efficient use of PCB area. 2.Area array access for high I/O device. 3.Allow for finer pitches. 4.Fewer joints. 5.Better performance of high frequency application. 6.FC is and will be lowest cost.

Abstract The thesis is aimed to analyze the flip chip in chip scale package (CSP) by finite element method incorporated with software ANSYS due to thermally cyclic loading. The coefficient of thermal expansion (CTE) of underfill and different mechanical properties of four kinds underfill-A, B, C, D and with/without metal cap are considered as parameters. The effects of above-mentioned parameters on package¡¦s displacement, strain and stress fields are studied. The results show that the maximum equivalent strain and stress take place at the interface between chip and underfill far away from the center of the whole package and on the top of the most outside solder bump in the solder joint. The larger the CTE of underfill is, the larger the maximum equivalent strain and stress are. Package with metal cap can reduce the displacement to almost half or more of that without cap, but increase the values of maximum equivalent strain and stress. No matter with metal cap or not, the underfill D is the best choice. Hence, the underfill material properties possess lower CTE and larger Young¡¦s modulus than those of solder bump.

The electromigration (EM) and chip-package interaction (CPI) reliability of flip chip packages with Cu pillar structures was investigated. First the EM-related characteristics of Cu pillars with solder tips were studied and compared with standard controlled collapse chip connection (C4) Pb-free solder joints. The simulation results revealed a significant reduction in the current crowding effect when C4 solder joints was replaced by Cu pillar structures. As a result, the current-induced Joule heating and local temperature gradients were reduced in the Cu pillar structure. This was followed by a study of the impact of the Cu pillar bumps on the mechanical reliability of low-k dielectrics. The CPI-induced crack driving force for delamination in the low-k interconnect structure was evaluated using a 3D sub-modeling technique. The energy release rate was found to increase significantly for packages with Cu pillar bumps compared with those with C4 Pb-free solder joints only. Structural optimization of Cu pillar bumps to improve the mechanical stability of packages with low-k chips was discussed. / text

Dissertation (Ph.D.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references (p.91-95).

Thesis(M.S.)--Auburn University, 2007. / Abstract. Vita. Includes bibliographic references.

Dissertation (Ph.D.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references.

Dissertation (Ph.D.)--Auburn University, 2006. / Abstract. Vita. Includes bibliographic references.

Techn. Universiẗat, Diss., 2005--Berlin.