Digital Signal Processors (DSPs) have been an important component of all signal processing systems for over two decades now. Some of the obvious advantages of digital signal processing are the flexibility to make specific changes in the processing functions through hardware or software programming, faster processing speeds of the DSPs, cheaper storage, and retrieval of digital information and lower sensitivity to electrical noise. The explosive growth of wireless and signal processing applications has resulted in an increasing demand for such systems with low cost, low power consumption, and small form factors. With high--level of integration to single--chip systems, power consumption becomes a very important concern to be addressed. Intermediate--Frequency (IF) band signal processing requires the use of an array of DSPs, operating in parallel, to meet the speed requirements. This is a power intensive approach and makes use of certain communication schemes impractical in applications where power budget is limited. The front--end ADC and back--end DAC converters required in these systems become expensive when the signal is of wideband nature and a greater resolution is required. We present techniques to use floating--gate devices to implement signal processing systems in the analog domain in a power efficient and cost effective manner. Use of floating--gate devices mitigates key limitations in analog signal processing such as the lack of flexibility to specific changes in processing functions and the lack of programmability. This will impact the way a variety of signal processing systems are designed currently. It also enables array signal processing to be done in an area efficient manner. As will be shown through sample applications, this methodology promises to replace expensive wideband ADC and DAC converters with relatively easy to implement baseband data converters and an array of power intensive high speed DSPs with baseband DSPs. This approach is especially beneficial for portable systems where a lot of applications are running from a single battery.

The increasing demands on higher density, lower cost, higher speed, better endurance and longer retention has push flash memory technology, which is predominant and the driving force of the semiconductor nonvolatile memory market in recent years, to the position facing great challenges. However, the conventional flash memory technology using continuous highly doped polysilicon as floating gate, which is the most common in today’s commercial market, can't satisfy these demands, with the transistor size continuously scaling down beyond 32 nm. Nanocrystal floating gate flash memory and SONOS-type flash memory are considered among the most promising approaches to extend scalability and performance improvement for next generation flash memory. This dissertation addresses the issues that have big effects on nanocrystal floating gate flash memory and SONOS-type flash memory performances. New device structures and new material compatible to CMOS flow are proposed and demonstrated as potential solutions for further device performance improvement. First, the effect of nanocrystal-high k dielectric interface quality on nanocrystal flash memory performance is studied. By using germanium-silicon core-shell nanocrystals or ruthenium nanocrystals buried in HfO₂ as charge storage nodes, high interface quality has been achieved, leading to promising memory device performance. Next, another crucial challenge for nanocrystal flash memory on how to deposit uniformly distributed nanocrystal matrix in good shape and size control with high density is discussed. Using protein GroEL to obtain well ordered high density nanocrystal pattern, a flash memory device with Ni nanocrystals buried in HfO₂ is demonstrated. For this technique, the nanocrystal size is restricted to the GroEL's central cavity size and the density is limited by protein template. To overcome this limitation, a novel method using self-assembled Co-SiO₂ nanocrystals as charge storage nodes is demonstrated. Separated by thin SiO₂, these nanocrystals can form close packed form to achieve ultrahigh density. Finally, charge trapping layer band engineering is proposed for SONOS-type memory for better memory performance. By manipulating the pulse ratio of Hf and Al precursor during ALD deposition, the band diagram of Hf[subscript x]Al[subscript y]O charge trapping layer is optimized to have a Hf : Al ratio 3:1 at bottom and 1:3 at the top, leading to better trade-off between programming and retention for the of memory device. / text

Analog Computing Arrays (ACAs) provide a computation system capable of performing a large number of multiply and add operations in an analog form. This system can therefore implement several computation algorithms that are currently realized using Digital Signal Processors (DSPs) who have an analogues accumulate and add functionality. DSPs are generally preferred for signal processing because they provide an environment that permits programmability once fabricated. ACA systems propose to offer similar functionality by providing a programmable and reconfigurable analog system. ACAs inherent parallelism and analog efficiency present several advantages over DSP implementations of the same systems. The computation power of an ACA system is directly proportional to the number of computing elements used in the system. Array size is limited by the number of computation elements that can be managed in an array. This number is continually growing and as a result, is permitting the realization of signal processing systems such as real-time speech recognition, image processing, and many other matrix like computation systems. This research provides a systematic process to implement, program, and use the computation elements in large-scale Analog Computing Arrays. This infrastructure facilitates the incorporation of ACA without the current headaches of programming large arrays of analog floating-gates from off-chip, currently using multiple power supplies, expensive FPGA controllers/computers, and custom Printed Circuit Board (PCB) systems. Proof of the flexibility and usefulness of ACAs has been demonstrated by the construction of two systems, an Analog Fourier Transform and a Vector Quantizer.

This thesis examines a floating gate device (FGD) structure available under standard (digital) CMOS manufacturing processes and puts forth two applications for these devices. The first application is the creation of a tunable current mirror. Inclusion of the FGD structure allows the legs of the mirror to be electronically tweaked to compensate for mismatch. Experimental data is presented on this device structure?s performance. The second application explores using the FGD structure as a tunable resistor. Operation of the FGD in this manner creates the possibility of an electrically tunable beta-multiplier current reference. This tunability allows theoretical adjustment of both the generated reference current as well as a selectable temperature performance. Experimental data of obtained resistor values is presented with simulation results of the entire circuit.

A method of synthesizing and controlling the size of germanium nanocrystals is developed. A tri-layer metal-insulator-semiconductor (MIS) memory device structure comprising of a thin (~5nm) silicon dioxide (SiO₂) layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO₂ of varying thickness (3 - 6 nm) deposited using a radio frequency (rf) co-sputtering technique, and a capping SiO₂ layer (50nm) deposited using rf sputtering is investigated. It was verified that the size of germanium (Ge) nanocrystals in the vertical z-direction in the trilayer memory device was controlled by varying the thickness of the middle (cosputtered Ge+SiO₂) layer. From analyses using transmission electron microscopy and capacitance-voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix. / Singapore-MIT Alliance (SMA)

The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulator-semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO₂ co-sputtered middle layer (i.e., lower Ge concentration), a higher charge storage capability was obtained than with devices with a thinner RTO layer, and the charge retention time was found to be less than in devices with a thicker RTO layer. / Singapore-MIT Alliance (SMA)

This thesis presents a new simulation model for floating gate transistor (FGMOS) in nanometer scale technology where the transistors suffer from non-negligible gate leakage current due to the very thin Silicon oxide (SiO2) layer. The new FGMOS simulation model is used for transient and DC simulation and with any industry standard simulators such as Spector and various SPICE programs (i.e. HSPICE, WinSPICE, etc.). This model can be used for any technology that has SiO2 thickness less than 3nm and suffer from gate leakage current with no changes to the model itself; however, minimal changes need to be done to the gate tunnelling cell to comply with the technology parameters where the gate tunnelling current exponentially increases as tox decreases.

A systematic approach has been used to optimise the fabrication process of pentacene-based nonvolatile organic thin film memory transistors (OTFMTs) operating at low programming voltages. In the first part of this work, reliable, reproducible and hysteresis free organic metal-insulator-semiconductor (OMIS) devices and organic thin film transistors (OTFTs) were fabricated and characterised. All devices were based on poly(methyl methacrylate) (PMMA) and poly(vinyl phenol) (PVP) as the organic insulators. The second part of this work focused on optimising the evaporation parameters to fabricate high-performance pentacene-based devices. About 50 nm thickness of pentacene film with a deposition rate of 0.03 nm s-1 on ~ 300 nm of PMMA was found to produce large, uniform and condense grains leading to high quality devices. OTFTs with high mobility of 1.32 cm2 V−1 s−1, on/off current ratio of 106, and negligible hysteresis and leakage current were demonstrated. The effect of the environment on the OTFTs obehaviour was also investigated. The bias stress effect was also investigated in terms of threshold voltage shift ΔVT at various conditions and times. The results show ΔVT increases with the increase of stress voltage. A negligible hysteresis is evident between the forward and reverse direction of the transfer characteristics and the shape of the transfer characteristics does not change with the bias stress. Floating gate memory structures with thin layer of gold, gold nanoparticles (AuNPs) and single walled carbon nanotubes (SWCNTs) were fabricated and characterised during this investigation. Hysteresis in memory structures was a clear indication of the memory effect and charge storage in these devices. Also, the hysteresis was centred close to 0 V for SWCNTs-based structures, which indicate that a low operation voltage is needed to charge the devices. A memory window of about 40 V was observed for AuNPs-based memory devices based on PVP; while the memory windows for devices based on PMMA with thin layer of Au and AuNPs floating gates were 22 V and 32 V, respectively. The electrical properties of the OTFMTs were improved by the use of the Au nanoparticles as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate was charged and discharged, resulting in a clear shift in the threshold voltage of the memory transistors. Negative and positive pulses of 1 V resulted in clear write and erase states, respectively. Additionally, these organic memory transistors exhibited rather high carrier mobility of about μ = 0.319 cm2 V-1 s-1. Furthermore the data retention and endurance measurements confirmed the non-volatile memory properties of the memory devices fabricated in this study.

A relatively new area of analog integrated circuits is emerging which is likely to have an impact on the signal processing area --analog floating-gate circuits. Analog floating- gate circuits have the potential to deliver more sophisticated signal processing at less power in a smaller space. This is the result of a novel application of digital memory technology -- the floating-gate MOSFET, that is used as an analog memory and computational device. Critical to the success of analog floating-gate circuits is on-chip programming. After investigating integrated schemes for DC-DC converters to generate the necessary voltages on chip, this research focuses on charge pumps that are integrated into the programming structure of floating-gate circuits. The impact of this research is far reaching since programmability is an indispensable feature of analog floating-gate circuits. This research lays the foundation for meeting the requirement of on-chip programming. Charge pumps will eliminate the need for high voltages to be externally supplied or regulated for analog floating-gate circuits. To the design engineer, the utilization of floating-gate circuits will look identical to their non floating-gate counterparts in terms of the value and number of supply voltages. In addition, the integration of on-chip DC-DC converters will reduce pin count, reduce board space for the implementation of the chip and facilitate distributed on chip power supplies for mixed signal integrated circuits.

The subthreshold region of operation has simple physics which allows for a balanced-force approach to behavioral modeling that has shown to be robust to temperature, and a model that encapsulates MOSFET behavior across all operational regions has been developed. The subthreshold region of operation also allows for injection of charge onto floating nodes that allows for persistent storage that can be used in a variety of applications. The combination of charge storage and device modeling has allowed for the development of programmable circuits for digital applications.