Research presented in this thesis provides a substantial leap from the study of interesting device physics to fully adaptive analog networks and lays a solid foundation for future development of large-scale, compact, low-power adaptive parallel analog computation systems. The investigation described here started with observation of this potential learning capability and led to the first derivation and characterization of the floating-gate pFET correlation learning rule. Starting with two synapses sharing the same error signal, we progressed from phase correlation experiments through correlation experiments involving harmonically related sinusoids, culminating in learning the Fourier series coefficients of a square wave cite{kn:Dugger2000}. Extending these earlier two-input node experiments to the general case of correlated inputs required dealing with weight decay naturally exhibited by the learning rule. We introduced a source-follower floating-gate synapse as an improvement over our earlier source-degenerated floating-gate synapse in terms of relative weight decay cite{kn:Dugger2004}. A larger network of source-follower floating-gate synapses was fabricated and an FPGA-controlled testboard was designed and built. This more sophisticated system provides an excellent framework for exploring applications to multi-input, multi-node adaptive filtering applications. Adaptive channel equalization provided a practical test-case illustrating the use of these adaptive systems in solving real-world problems. The same system could easily be applied to noise and echo cancellation in communication systems and system identification tasks in optimal control problems. We envision the commercialization of these adaptive analog VLSI systems as practical products within a couple of years.

This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic approach to simultaneously apply analog, digital, and neuromorphic techniques to solving general problems. Typically, this is a very difficult task, and one that few attempt to undertake. However, when done right, solutions can be found with orders-of-magnitude improvement over existing solutions restricted to using only one type computational domain. To that end, I have helped build large and complicated reconfigurable systems (and software tools for helping to use these systems) capable of implementing solutions to problems in all three of those domains simultaneously. These systems are used to explore and implement these cross domain solutions to difficult problems. The earlier work was involved with simply applying floating-gate technology to improving the building blocks of digital systems. Through that early work a new logic family built from floating-gate transistors was discovered, a Logical Effort compatible power analysis technique was developed, and low power floating-gate based FPGA was implemented. This work was then merged with existing research in the group involving solving problems using reconfigurable analog, and neuromorphic techniques. Thus converging on the mentioned systems that allow one to solve problems using techniques from all three domains: analog, neuromorphic, and digital.

This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.

Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.

Camera-on-a-chip systems have tried to include carefully chosen signal processing units for better functionality, performance and also to broaden the applications they can be used for. Image processing sensors have been possible due advances in CMOS active pixel sensors (APS) and neuromorphic focal plane imagers. Some of the advantages of these systems are compact size, high speed and parallelism, low power dissipation, and dense system integration. One can envision using these chips for portable and inexpensive video cameras on hand-held devices like personal digital assistants (PDA) or cell-phones In neuromorphic modeling of the retina it would be very nice to have processing capabilities at the focal plane while retaining the density of typical APS imager designs. Unfortunately, these two goals have been mostly incompatible. We introduce our MAtrix Transform Imager Architecture (MATIA) that uses analog floating--gate devices to make it possible to have computational imagers with high pixel densities. The core imager performs computations at the pixel plane, but still has a fill-factor of 46 percent - comparable to the high fill-factors of APS imagers. The processing is performed continuously on the image via programmable matrix operations that can operate on the entire image or blocks within the image. The resulting data-flow architecture can directly perform all kinds of block matrix image transforms. Since the imager operates in the subthreshold region and thus has low power consumption, this architecture can be used as a low-power front end for any system that utilizes these computations. Various compression algorithms (e.g. JPEG), that use block matrix transforms, can be implemented using this architecture. Since MATIA can be used for gradient computations, cheap image tracking devices can be implemented using this architecture. Other applications of this architecture can range from stand-alone universal transform imager systems to systems that can compute stereoscopic depth.

This research focuses on biologically inspired audio signal processing using programmable analog circuitry. This research is inspired by the biology of the human cochlea since biology far outperforms any engineered system at converting audio signals into meaningful electrical signals. The human cochlea efficiently decomposes any sound into the respective frequency components by harnessing the resonance nature of the basilar membrane, essentially forming a bank of bandpass filters. In a similar fashion, this work revolves around developing a filter bank composed of continuous-time, low-power, analog bandpass filters that serve as the core front end to this silicon audio-processing system. Like biology, the individual bandpass filters are tuned to have narrow bandwidths, moderate amounts of resonance, and exponentially spaced center frequencies. This audio front end serves to efficiently convert incoming sounds into information useful to subsequent signal-processing elements, and it does so by performing a frequency decomposition of the waveform with extremely low-power consumption and real-time operation. To overcome mismatch and offsets inherent in CMOS processes, floating-gate transistors are used to precisely tune the time constants in the filters and to allow programmability of analog components.

Univ, Diss.--Kiel., 2007.

Techn. Hochsch., Diss., 2006--Aachen.

The emergence of novel electronic, optical and magnetic properties in ordered two-dimensional (2D) nanoparticle ensembles, due to collective dipolar interactions of surface plasmons or excitons or magnetic moments have motivated intense research efforts into fabricating functional nanostructure assemblies. Such functional assemblies (i.e., highly-integrated and addressable) have great potential in terms of device performance and cost benefits. Presently, there is a paradigm shift from lithography based top-down approaches to bottom-up approaches that use self-assembly to engineer addressable architectures from nanoscale building blocks. The objective of this dissertation was to develop appropriate processing tools that can overcome the common challenges faced in fabricating floating gate memory devices using self-assembled 2D metal nanoparticle arrays as charge storage nodes. The salient challenges being to synthesize monodisperse nanoparticles, develop large scale guided self-assembly processes and to integrate with Complementary Metal Oxide Semiconductor (CMOS) memory device fabrication processes, thereby, meeting the targets of International Technology Roadmap for Semiconductors (ITRS) – 2017, for non-volatile memory devices. In the first part of the thesis, a simple and robust process for the formation of wafer-scale, ordered arrays using dodecanethiol capped gold nanoparticles is reported. Next, the results of ellipsometric measurements to analyze the effect of excess ligand on the self-assembly of dodecanethiol coated gold nanoparticles at the air-water interface are discussed. In a similar vein, the technique of drop-casting colloidal solution is extended for tuning the interparticle spacing in the sub-20 nm regime, by altering the ligand length, through thiol-functionalized polystyrene molecules of different molecular weights. The results of characterization, using the complementary techniques of Atomic Force Microscopy (AFM) and Field-Emission Scanning Electron Microscopy (FESEM), of nanoparticle arrays formed by polystyrene thiol (average molecular weight 20,000 g/mol) grafted gold nanoparticles (7 nm diameter) on three different substrates and also using different solvents is then reported. The substrate interactions were found to affect the interparticle spacing in arrays, changing from 20 nm on silicon to 10 nm on a water surface; whereas, the height of the resultant thin film was found to be independent of substrate used and to correlate only with the hydrodynamic diameter of the polymer grafted nanoparticle in solution. Also, the mechanical properties of the nanoparticle thin films were found to be significantly altered by such compression of the polymer ligands. Based on the experimental data, the interparticle spacing and packing structure in these 2D arrays, were found to be controlled by the substrate, through modulation of the disjoining pressure in the evaporating thin film (van der Waals interaction); and by the solvent used for drop casting, through modulation of the hydrodynamic diameter. This is the first report on the ability to vary interparticle spacing of metal nanoparticle arrays by tuning substrate interactions alone, while maintaining the same ligand structure. A process to fabricate arrays with square packing based on convective shearing at a liquid surface induced by miscibility of colloidal solution with the substrate is proposed. This obviates the need for complex ligands with spatially directed molecular binding properties. Fabrication of 3D aggregates of polymer-nanoparticle composite by manipulating solvent-ligand interactions is also presented. In flash memory devices, charges are stored in a floating gate separated by a tunneling oxide layer from the channel, and the tunneling oxide thickness is scaled down to minimize power consumption. However, reduction in tunneling oxide thickness has reached a stage where data loss can occur due to random defects in the oxide. Using metal nanoparticles as charge-trapping nodes will minimize the data loss and enhance reliability by compartmentalizing the charge storage. In the second part of the thesis, a scalable and CMOS compatible process for fabricating next-generation, non-volatile, flash memory devices using the self-assembled 2D arrays of gold nanoparticles as charge storage nodes were developed. The salient features of the fabricated devices include: (a) reproducible threshold voltage shifts measured from devices spread over cm2 area, (b) excellent retention (>10 years) and endurance characteristics (>10000 Program/Erase cycles). The removal of ligands coating the metal nanoparticles using mild RF plasma etching was found, based on FESEM characterization as well as electrical measurements, to be critical in maintaining both the ordering of the nanoparticles and charge storage capacity. Results of Electrostatic Force Microscope (EFM) measurements are presented, corroborating the need for ligand removal in obtaining reproducible memory characteristics and reducing vertical charge leakage. The effect of interparticle spacing on the memory characteristics of the devices was also studied. Interestingly, the arrays with interparticle spacing of the order of nanoparticle diameter (7 nm) gave rise to the largest memory window, in comparison with arrays with smaller (2 nm) or larger interparticle spacing (20 nm). The effect of interparticle spacing and ligand removal on memory characteristics was found to be independent of different top-oxide deposition processes employed in device fabrication, namely, Radio-frequency magnetron sputtering (RF sputtering), Atomic Layer Deposition (ALD) and electron-beam evaporation. In the final part of the thesis, a facile method for transforming polydisperse citrate capped gold nanoparticles into monodisperse gold nanoparticles through the addition of excess polyethylene glycol (PEG) molecules is presented. A systematic study was conducted in order to understand the role of excess ligand (PEG) in enabling size focusing. The size focusing behavior due to PEG coating of nanoparticles was found to be different for different metals. Unlike the digestive ripening process, the presence of PEG was found to be critical, while the thiol functionalization was not needed. Remarkably, the amount of adsorbed carboxylate-PEG mixture was found to play a key role in this process. The stability of the ordered nanoparticle films under vacuum was also reported. The experimental results of particle ripening draw an analogy with the well-established Pechini process for synthesizing metal oxide nanostructures. The ability to directly self-assemble nanoparticles from the aqueous phase in conjunction with the ability to transfer these arrays to any desired substrate using microcontact printing can foster the development of applications ranging from flexible electronics to sensors. Also, this approach in conjunction with roll-to-roll processing approaches such as doctor-blade casting or convective assembly can aid in realizing the goal of large scale nanostructure fabrication without the utilization of organic solvents.

Nesta dissertação é apresentado o estudo dos transistores de porta flutuante (Floating Gate Transistor - FG Transistor), sua modelagem, e a análise do efeito da dose de ionização total (Total Ionizing Dose- TID) sobre os transistores FG. Para isto foi procurado e implementado um modelo de simulação elétrica do transistor FG em condições de leitura (análise DC), baseado no cálculo quantitativo da tensão na porta flutuante em função das tensões nos terminais do transistor, no valor de carga armazenado na porta flutuante e nos coeficientes de acoplamento capacitivo que apresentam este tipo de dispositivos. Para a análise do efeito TID, a tensão limiar do transistor MOS foi variada usando o método de simulação Monte Carlo, tendo em conta as variações da tensão limiar que apresentam os transistores FG submetidos na radiação ionizante. O estudo obteve como resultado a confirmação da perda de carga do FG à medida que é incrementada a dose de radiação, o que implica uma alteração na característica de retenção de carga que caracteriza as células de memórias não voláteis (Non Volatile Memory - NVM). / In this dissertation work, a study of the the floating gate Transistor (FG transistor) performed. The focus in the electrical modeling, and the analysis of the impact of the Total Ionizing Dose (TID) on the electrical performance of the device. Aiming electrical level simulation, different electric simulation models for the FG transistor in read conditions (DC analysis) were evaluated and the model best suited for implementation into the simulation tool was selected. The selected model is based on Floating Gate voltage calculation as a function of polarization voltage of the FG transistor terminals, the stored charge value in the Floating Gate and the capacitive coupling coefficient presented by this device. For the TID analysis the threshold voltage of the MOS transistor was shifted by means of a Monte Carlo simulation method, considering the threshold voltage variations when the FG transistor is subjected to the ionizing radiation.The analysis lead to the confirmation that the loss charge stored in the FG increases with the radiation dose, affecting the retention characteristics of the memory cells.