This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.

Nesta dissertação é apresentado o estudo dos transistores de porta flutuante (Floating Gate Transistor - FG Transistor), sua modelagem, e a análise do efeito da dose de ionização total (Total Ionizing Dose- TID) sobre os transistores FG. Para isto foi procurado e implementado um modelo de simulação elétrica do transistor FG em condições de leitura (análise DC), baseado no cálculo quantitativo da tensão na porta flutuante em função das tensões nos terminais do transistor, no valor de carga armazenado na porta flutuante e nos coeficientes de acoplamento capacitivo que apresentam este tipo de dispositivos. Para a análise do efeito TID, a tensão limiar do transistor MOS foi variada usando o método de simulação Monte Carlo, tendo em conta as variações da tensão limiar que apresentam os transistores FG submetidos na radiação ionizante. O estudo obteve como resultado a confirmação da perda de carga do FG à medida que é incrementada a dose de radiação, o que implica uma alteração na característica de retenção de carga que caracteriza as células de memórias não voláteis (Non Volatile Memory - NVM). / In this dissertation work, a study of the the floating gate Transistor (FG transistor) performed. The focus in the electrical modeling, and the analysis of the impact of the Total Ionizing Dose (TID) on the electrical performance of the device. Aiming electrical level simulation, different electric simulation models for the FG transistor in read conditions (DC analysis) were evaluated and the model best suited for implementation into the simulation tool was selected. The selected model is based on Floating Gate voltage calculation as a function of polarization voltage of the FG transistor terminals, the stored charge value in the Floating Gate and the capacitive coupling coefficient presented by this device. For the TID analysis the threshold voltage of the MOS transistor was shifted by means of a Monte Carlo simulation method, considering the threshold voltage variations when the FG transistor is subjected to the ionizing radiation.The analysis lead to the confirmation that the loss charge stored in the FG increases with the radiation dose, affecting the retention characteristics of the memory cells.

Nesta dissertação é apresentado o estudo dos transistores de porta flutuante (Floating Gate Transistor - FG Transistor), sua modelagem, e a análise do efeito da dose de ionização total (Total Ionizing Dose- TID) sobre os transistores FG. Para isto foi procurado e implementado um modelo de simulação elétrica do transistor FG em condições de leitura (análise DC), baseado no cálculo quantitativo da tensão na porta flutuante em função das tensões nos terminais do transistor, no valor de carga armazenado na porta flutuante e nos coeficientes de acoplamento capacitivo que apresentam este tipo de dispositivos. Para a análise do efeito TID, a tensão limiar do transistor MOS foi variada usando o método de simulação Monte Carlo, tendo em conta as variações da tensão limiar que apresentam os transistores FG submetidos na radiação ionizante. O estudo obteve como resultado a confirmação da perda de carga do FG à medida que é incrementada a dose de radiação, o que implica uma alteração na característica de retenção de carga que caracteriza as células de memórias não voláteis (Non Volatile Memory - NVM). / In this dissertation work, a study of the the floating gate Transistor (FG transistor) performed. The focus in the electrical modeling, and the analysis of the impact of the Total Ionizing Dose (TID) on the electrical performance of the device. Aiming electrical level simulation, different electric simulation models for the FG transistor in read conditions (DC analysis) were evaluated and the model best suited for implementation into the simulation tool was selected. The selected model is based on Floating Gate voltage calculation as a function of polarization voltage of the FG transistor terminals, the stored charge value in the Floating Gate and the capacitive coupling coefficient presented by this device. For the TID analysis the threshold voltage of the MOS transistor was shifted by means of a Monte Carlo simulation method, considering the threshold voltage variations when the FG transistor is subjected to the ionizing radiation.The analysis lead to the confirmation that the loss charge stored in the FG increases with the radiation dose, affecting the retention characteristics of the memory cells.

Nesta dissertação é apresentado o estudo dos transistores de porta flutuante (Floating Gate Transistor - FG Transistor), sua modelagem, e a análise do efeito da dose de ionização total (Total Ionizing Dose- TID) sobre os transistores FG. Para isto foi procurado e implementado um modelo de simulação elétrica do transistor FG em condições de leitura (análise DC), baseado no cálculo quantitativo da tensão na porta flutuante em função das tensões nos terminais do transistor, no valor de carga armazenado na porta flutuante e nos coeficientes de acoplamento capacitivo que apresentam este tipo de dispositivos. Para a análise do efeito TID, a tensão limiar do transistor MOS foi variada usando o método de simulação Monte Carlo, tendo em conta as variações da tensão limiar que apresentam os transistores FG submetidos na radiação ionizante. O estudo obteve como resultado a confirmação da perda de carga do FG à medida que é incrementada a dose de radiação, o que implica uma alteração na característica de retenção de carga que caracteriza as células de memórias não voláteis (Non Volatile Memory - NVM). / In this dissertation work, a study of the the floating gate Transistor (FG transistor) performed. The focus in the electrical modeling, and the analysis of the impact of the Total Ionizing Dose (TID) on the electrical performance of the device. Aiming electrical level simulation, different electric simulation models for the FG transistor in read conditions (DC analysis) were evaluated and the model best suited for implementation into the simulation tool was selected. The selected model is based on Floating Gate voltage calculation as a function of polarization voltage of the FG transistor terminals, the stored charge value in the Floating Gate and the capacitive coupling coefficient presented by this device. For the TID analysis the threshold voltage of the MOS transistor was shifted by means of a Monte Carlo simulation method, considering the threshold voltage variations when the FG transistor is subjected to the ionizing radiation.The analysis lead to the confirmation that the loss charge stored in the FG increases with the radiation dose, affecting the retention characteristics of the memory cells.

Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.

La miniaturisation des composants et l’amélioration des performances des circuits intégrés (ICs) sont dues aux progrès liés au procédé de fabrication. Malgré le nombre de technologie existante, la technologie CMOS est la plus utilisée. Dans le cadre du développement de la technologie CMOS 90nm à double niveau de poly, des recherches sur l’introduction de techniques innovantes de procédé de fabrication et d’une nouvelle architecture de transistor MOS à tension de seuil ajustable ont été menées dans le but d’améliorer les performances des ICs. Une première étude sur l’implémentation des effets de pointe dans les ICs, en particulier pour les mémoires non volatiles est entreprise. Un nouveau procédé de fabrication permettant d’obtenir des pointes dans un matériau est proposé. Il est démontré le gain en courant tunnel obtenu sur une structure pointue par rapport à une structure plane. Une seconde étude est orientée sur le développement d’une nouvelle technique de « patterning ». Les techniques de « patterning » permettent de réduire les dimensions de la photolithographie sans utiliser de masque ayant des dimensions agressives. Les avantages de cette nouvelle technique aux niveaux de sa mise en œuvre et de la suppression des problèmes d’alignement sont présentés. Une dernière étude sur le développement d’un transistor à tension de seuil ajustable est développée. Il est démontré l’avantage de ce composant par rapport aux autres composants à tension de seuil ajustable. La réalisation du modèle et des premières simulations électriques de circuit élémentaire à base de se composant sont présentés. L’amélioration de certaines performances des circuits élémentaire est démontrée. / The component miniaturization and the circuit performance improvement are due to the progress related to the manufacturing process. Despite the number of existing technology, the CMOS technology is the most used. In the 90nm CMOS technology development, with a double poly-silicon level, the research on the introduction of innovative manufacturing process techniques and a new architecture of MOS transistor with an adjustable threshold voltage are carried out to improve the integrated circuit performances. A first study, on the peak effect implementation in the integrated circuits, particularly in the non-volatile memories is undertaken. A new process to obtain a peak effect in a material is proposed. It is shown the tunnel current gain obtained on a peak structure compared with a planar structure. A second study is focused on the development of a new patterning technique. The patterning techniques allow to reduce the photolithography dimensions without using an aggressive mask. The advantages of this new technique in terms of its implementation and the suppression of alignment problems are presented. A last study on the development of a MOS transistor with an adjustable threshold voltage is developed. It is shown the advantage of this component relative to the other components with an adjustable threshold voltage. The model implementation and the first electrical simulations of elementary circuits composed with this new component are presented. The performance improvement of some elementary circuits is demonstrated.