This thesis tackles the problem of high-speed data communication over wireline channels. Particular attention is paid to backplane channels which have impedance discontinuities and high-frequency loss. These channels require extra equalization effort in order to produce an open eye diagram at the receiver. Three signal processing techniques were investigated in the pursuit of higher data rates over backplane channels: transmit-side FIR filter equalization with variable tap spacing, bidirectional communication using frequency-division multiplexing, and an ADC-based receiver to provide a capability for non-linear equalization. The ADC presented here is a 5-bit flash ADC intended to be time-interleaved to attain a sufficient data rate. This ADC uses redundant comparators to obtain sufficient resolution without an explicit threshold tuning circuit. A resonant clocking line is used to reduce power and increase the maximum clock frequency.

This thesis tackles the problem of high-speed data communication over wireline channels. Particular attention is paid to backplane channels which have impedance discontinuities and high-frequency loss. These channels require extra equalization effort in order to produce an open eye diagram at the receiver. Three signal processing techniques were investigated in the pursuit of higher data rates over backplane channels: transmit-side FIR filter equalization with variable tap spacing, bidirectional communication using frequency-division multiplexing, and an ADC-based receiver to provide a capability for non-linear equalization. The ADC presented here is a 5-bit flash ADC intended to be time-interleaved to attain a sufficient data rate. This ADC uses redundant comparators to obtain sufficient resolution without an explicit threshold tuning circuit. A resonant clocking line is used to reduce power and increase the maximum clock frequency.

Research presented in this thesis provides a substantial leap from the study of interesting device physics to fully adaptive analog networks and lays a solid foundation for future development of large-scale, compact, low-power adaptive parallel analog computation systems. The investigation described here started with observation of this potential learning capability and led to the first derivation and characterization of the floating-gate pFET correlation learning rule. Starting with two synapses sharing the same error signal, we progressed from phase correlation experiments through correlation experiments involving harmonically related sinusoids, culminating in learning the Fourier series coefficients of a square wave cite{kn:Dugger2000}. Extending these earlier two-input node experiments to the general case of correlated inputs required dealing with weight decay naturally exhibited by the learning rule. We introduced a source-follower floating-gate synapse as an improvement over our earlier source-degenerated floating-gate synapse in terms of relative weight decay cite{kn:Dugger2004}. A larger network of source-follower floating-gate synapses was fabricated and an FPGA-controlled testboard was designed and built. This more sophisticated system provides an excellent framework for exploring applications to multi-input, multi-node adaptive filtering applications. Adaptive channel equalization provided a practical test-case illustrating the use of these adaptive systems in solving real-world problems. The same system could easily be applied to noise and echo cancellation in communication systems and system identification tasks in optimal control problems. We envision the commercialization of these adaptive analog VLSI systems as practical products within a couple of years.

One of two project reports. Part B can be found at: / No abstract was provided. / Thesis / Master of Engineering (ME)

This thesis examines the design of high-speed wireline receivers that can be adapted to a variety of operating conditions. In particular, the ability to adapt to varying received signal strengths, channel losses and operating frequencies is explored. In order to achieve this flexibility, this thesis examines several key components of such a receiver. First, a 15 Gb/s preamplifier with 10-dB gain control for the input stage of an analog front end (AFE) is presented that automatically adjusts its power consumption to suit the gain and linearity requirements of the AFE for various received signal strengths. The gain of this preamplifier, along with the amount of peaking delivered by a linear equalizer in the AFE are controlled using a new adaptation technique, which adds only a small amount of overhead to the receiver. This adaptation scheme is able to sense changes in the received signal conditions and automatically adjust the equalization and gain of the AFE in order to optimize the vertical opening of the received eye. In addition, this thesis presents the first clock multiplier with both a wide operating frequency range and the ability to transition between completely off and fully operational modes in under 10 cycles of the reference clock. This multiplier relies on the careful use of several injection-locked oscillators (ILOs) with an aggregate lock range of 55.7% of the 3.16-GHz centre frequency. The design of these ILOs was facilitated by the use of a new method for modeling the injection locking behaviour of oscillators. This model differs from existing techniques in the way that it relies on the simulated response of an oscillator to injected stimuli, instead of complex equations using quasi-physical parameters, to predict the behaviour of an ILO.

This thesis examines the design of high-speed wireline receivers that can be adapted to a variety of operating conditions. In particular, the ability to adapt to varying received signal strengths, channel losses and operating frequencies is explored. In order to achieve this flexibility, this thesis examines several key components of such a receiver. First, a 15 Gb/s preamplifier with 10-dB gain control for the input stage of an analog front end (AFE) is presented that automatically adjusts its power consumption to suit the gain and linearity requirements of the AFE for various received signal strengths. The gain of this preamplifier, along with the amount of peaking delivered by a linear equalizer in the AFE are controlled using a new adaptation technique, which adds only a small amount of overhead to the receiver. This adaptation scheme is able to sense changes in the received signal conditions and automatically adjust the equalization and gain of the AFE in order to optimize the vertical opening of the received eye. In addition, this thesis presents the first clock multiplier with both a wide operating frequency range and the ability to transition between completely off and fully operational modes in under 10 cycles of the reference clock. This multiplier relies on the careful use of several injection-locked oscillators (ILOs) with an aggregate lock range of 55.7% of the 3.16-GHz centre frequency. The design of these ILOs was facilitated by the use of a new method for modeling the injection locking behaviour of oscillators. This model differs from existing techniques in the way that it relies on the simulated response of an oscillator to injected stimuli, instead of complex equations using quasi-physical parameters, to predict the behaviour of an ILO.

With rising fuel prices, increasing electrification, and imminent fines on CO2 emission within the EU, the requirement for energy and cost efficient supply concepts is becomingmore and more important in the automotive industry. This thesis presents an assessmentof, and improvement for energy and cost efficient power supply concepts for low-end automotiveand light e-mobility electronic control units, containing small µCs, and analogand logic components. Specifically, linear regulators, synchronous and non-synchronous buck converters, andswitched capacitor converters are investigated and assessed theoretically. The mostpromising concept, namely a discrete buck converter, is further studied using theoreticalassessment, experiment, and simulations. The key result of this work is a concept for replacing commonly used linear regulatorsin small electronic control units (ECUs) by a more efficient supply with only a smallcost adder. Specifically, since no low-end switched converter ICs are available today, wedeveloped a buck converter with discrete control circuit. This concept provides a cheap,yet efficient alternative to linear regulators for a wide range of applications. In addition,the application of this concept is supported by component selection criteria, and also bythe developed simulation models.

<p>Sensor technology is evolving rapidly, offering new opportunities for environmental data collection. Yet, despite the large number of sensors now available, there is a lack of logging platforms that can be used to operate these sensors in situ. To address this shortfall, River Restoration Intelligence and Verification (RRIV) has developed an environmental data logger that meets the needs of the environmental sensing community. This platform has several advantages that reduce the time, effort, and technical know-how required to deploy environmental sensors. An extensive low-power mode is available, and hardware such as a real-time clock with an independent power source is incorporated. A driver system has been developed that allows users to incorporate sensors into the platform with minimal effort. RRIV loggers also include a command line interface that allows user to add or remove sensors, calibrate sensors, or configure deployments without the need for C/C++ programming, something that is not possible with out-of-the-box microcontrollers such as Arduino and ST Nucleo products. The technology incorporated into RRIV and how it is applied and deployed in the field is described. This includes a description of power consumption. Protocols and descriptions of case construction are also included. RRIV loggers configured to monitor carbon dioxide and methane are used to demonstrate how this platform is used in the field.</p>

This report describes an ultrasound anemometer and its evaluation. This anemometer is a possible alternative for the automated weather stations which will be built in Africa as a part of WIMEA-ICT project. The project is done in cooperation with Norad and different universities in Africa and Norway. The report covers the assembly of the ultrasound anemometer and evaluation of both software and hardware in this embedded system. Two different type of the anemometer are assembled. The hardware and the software of the anemometers and the whole systems as embedded systems are tested. In addition, the whole system is analyzed and suggestions to increase the energy efficiency of the systems are given. / Den här rapporten beskriver en ultraljudsanemometer och en utvärdering av den. Denna anemometer är ett tänkbar alternativ för automatiserade väderstationer som ska upprättas i Afrika som en del av WIMEA-ICT projektet. Projektet sker i samarbete med Norad och olika universitet i Afrika och i Norden. Rapporten avhandlar hopsättningen av ultraljudsanemometern och utvärderingen av både hårdvara och mjukvara i detta inbyggda system. Två olika prototyper av anemometern monterades. Dessa testades ur aspekter som hårdvara, mjukvara samt i helhet som ett inbyggt system. Vidare gjordes en analys av hela systemet och förslag till energieffektivisering för systemet gavs.

Les objectifs de la thèse concernent l’optimisation du rendement énergétique, la minimisation de l’empreinte et du coût de l’alimentation en tension d’amplificateurs audio pour l’application casque des plateformes mobiles. Après une présentation du contexte des plateformes mobiles et des caractéristiques principales des amplificateurs audio dédiés, l’introduction conclut sur la nécessité d’une alimentation en tensions bipolaires, symétriques et donne les spécifications principales d’une telle alimentation en énergie électrique. Le chapitre d’état de l’art présente dans un premier temps les architeture les plus compétitves permettant de générer deux tensions symétriques. Une figure de mérite englobe le rendement énergétique, l’empreinte sur la plateforme et le coût en composants passifs externes de chacune des solutions présentées. Une architecture de convertisseur utilisant une seule inductance pour obtenir des tensions régulées symétriques se révelle etre un candidat interessant pour l’alimentation des amplificateurs dédiés aux casques audio. Cette architecture à été démontrée mais cependant loin des spécifications de l’application casque audio. Basée sur cette architecture, le chapitre troisième présente un étage de puissance et ses modes de conduction correspondant aux spécifications de l’application casque audio. Des détails concernent en particulier la conception des interrupteurs ainsi que la stratégie d’asservissement et de régulation. Des premières estimations de rendement sont évaluées dans les pires cas de fonctionnement. Très tôt dans le déroulement de la thèse, il y a eu une opportunité de tester l’étage de puissance en technologie CMOS 130nm. Le chapitre 4 présente l’implémentation du convertisseur sur un circuit de test. Le convertisseur est embarqué notamment à côté d’un amplificateur audio dédié, autorisant des tests plus proches de la réalité d’usage. Les campagnes de mesures ont concerné les aspects fonctionnels et les valeurs de rendement. Les résultats sont encourageants mais confirment les éléments non optimaux du dispositif. Dans l’idée d’un second silicium, le chapitre cinquième décrit plus théoriquement l’approche d’asservissement et de régulation et met en évidence des cas critiques, peu probables mais concrets, liés à l’évaluation sur des profils de charge réelle du convertisseur. Des simulations permettent de transformer un flux audio en courbe de courant absorbé par l’amplificateur audio, c’est-à-dire la charge réelle vue par le convertisseur de tensions symétriques. Le chapitre sixième décrit des améliorations à propos des modes de conduction, à savoir l’introduction des modes discontinu ou d’élimination d’impulsion (pulse skipping). Malheureusement une crise économique a barré l’accès à un silicium de validation finale. Le manuscrit est conclu par un rappel des résultats principaux et des perspectives. Les travaux ont fait l’objet de publications à des conférences internationales. / The objectives of this thesis were the optimization of the power efficiency and the minimization of the footprint area and cost of the integrated power supply of headset audio amplifiers on mobile platforms (fig. 1). The thesis took place in the Analog System Design group at ST Ericsson in strong collaboration with Ampere laboratory at INSA de Lyon. The french agency ANRT provided part of the project funding. The first chapter presents the current mobile platform context as well as the main characteristics of audio amplifiers driving headphones. This chapter concludes giving the need of a symmetrical power supply for the headset audio amplifiers and giving a set of electrical specifications for this power supply. The second chapter presents the state-of-the-art in terms of symmetrical power supply architectures able to fit the previously given characteristics and specifications. A set of key parameters based on the power efficiency, the relative silicon area, the relative external bill of material, the number of Input/Output pins and the external passive components area, is employed to benchmark all existing architectures to supply such audio amplifiers. This benchmark reveals the novel Single Inductor Bipolar Output (SIBO) converter as very promising. The similar existing circuits are also detailed and pros and cons of each one of them are discussed to define the most suited architecture. The third chapter proposes a dedicated power stage architecture and related conduction schemes. The design of the power stage is described as well as its dedicated control strategy. Some ideal efficiency estimations are given. The fourth chapter presents the realization of a first prototype, designed in a 130 nm ST Microelectronics CMOS process to be an early demonstrator of the architecture in chapter 3. Measurements on efficiency, control and transient performances are presented and discussed. This circuit embedded on the same die as an audio amplifier proves its effectiveness in supplying such a circuit. The fifth chapter presents a theoretical analysis of the feedback control of this SIBO converter. Mathematical linear model of the converter is derived to obtain its transfer function matrix, then the feedback structure design is defined thanks to dedicated mathematical tools. A set of classical PID controllers is proposed and validated with piecewise linear model while playing different audio popular songs. The sixth chapter describes the design of improvements of the first test chip as well as simulation results about these improvements. The main improvements presented in this chapter are a Discontinuous Conduction Mode (DCM) as well as a Pulse Skipping Mode (PSM). No silicon result can be presented here due to a budget restriction that impacted the course of the thesis. The final chapter is a discussion about the proposed solutions and some perspectives to the present work.