Τα τελευταία χρόνια η ανάγκη για αναλογικά ολοκληρωμένα κυκλώματα με χαμηλή τάση τροφοδοσίας και χαμηλή ισχύ γίνεται κάτι περισσότερο από επιτακτική. Ο βασικότερος λόγος για την ανάγκη αυτή είναι η ραγδαία ανάπτυξη από φορητές ηλεκτρονικές συσκευές για εφαρμογές πολυμέσων (laptops, netbooks, mobiles) έως ολοκληρωμένων συστημάτων βιοιατρικών εφαρμογών. Μάλιστα σε πολλές περιπτώσεις απαιτείται αυτές οι ηλεκτρονικές συσκευές να έχουν δυνατότητα διασύνδεσης σε ασύρματα δίκτυα (WLANs) και επομένως επιβάλλεται η ενσωμάτωση συστημάτων πομποδεκτών. Έτσι, οι απαιτήσεις για όσο το δυνατόν μικρότερη κατανάλωση και επομένως χαμηλότερη τροφοδοσία είναι επιβεβλημένες. Ένα από τα βασικότερα «δομικά» κυκλώματα σχεδίασης αναλογικών κυκλωμάτων είναι οι διαφορικοί ενισχυτές τάσης. Στην παρούσα διατριβή παρουσιάζονται πλήρεις λύσεις διαφορικών ενισχυτών χαμηλής τάσης τροφοδοσίας σε τυπική CMOS τεχνολογία των 0.35μm και 0.18μm. Οι προτεινόμενοι ενισχυτές σχεδιάστηκαν με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα (Bulk-driven technique). Αρχικά σχεδιάστηκαν διαφορικοί ενισχυτές τάσεις με τοπολογία αρνητικής αντίστασης στην βαθμίδα εισόδου. Με τον τρόπο αυτό έγινε αύξηση της μικρής διαγωγιμότητας εισόδου που παρουσιάζει η τεχνική οδήγησης τρανζίστορ από το υπόστρωμα. Έτσι, προέκυψαν πρωτότυπες δομές ενισχυτών με χαμηλή τροφοδοσία μέχρι και 0.8V. Οι επιδόσεις των ενισχυτών χαρακτηρίστηκαν από κατάλληλες προσομοιώσεις αλλά και από πειραματικές μετρήσεις καθώς κατασκευάστηκε ολοκληρωμένο κύκλωμα ενισχυτή. Η σύγκλιση των αποτελεσμάτων των προσομοιώσεων με των πειραματικών απέδειξε πως τόσο τα προτεινόμενα κυκλώματα όσο και η ίδια η τεχνική σχεδίασης αποτελούν σημαντική λύση όπου απαιτούνται διαφορικοί ενισχυτές τάσης χαμηλής τροφοδοσίας. Στη συνέχεια σχεδιάστηκε βαθμίδα διαφορικού ακόλουθου τάσης με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα και τροφοδοσία 1V. Η βαθμίδα αυτή χρησιμοποιήθηκε ως διαφορική βαθμίδα εισόδου διαφορικού ενισχυτή τάσης με τροφοδοσία 1V. Ο ενισχυτής αυτός λειτουργεί για μεταβολή του κοινού σήματος εισόδου μεταξύ των άκρων της τροφοδοσίας. Ο ακόλουθος τάσης τροποποιήθηκε κατάλληλα ώστε να λειτουργεί με τροφοδοσία 0.5V και χρησιμοποιήθηκε ως διαφορική βαθμίδα εισόδου σε διαφορικό ενισχυτή τάσης ίδιας τροφοδοσίας. Και οι δυο προτεινόμενες τοπολογίες ενισχυτών αποτελούν πλήρεις λύσεις για εφαρμογές ενισχυτών τάσης με χαμηλή και πολύ χαμηλή τροφοδοσία αντίστοιχα. Τέλος με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα σχεδιάστηκε ενισχυτής μεταβλητού κέρδους. Για το σκοπό αυτό αναπτύχθηκε τεχνική γραμμικής μεταβολής διαγωγιμότητας διαγωγών. Ο ενισχυτής μεταβλητού κέρδους που σχεδιάστηκε λειτουργεί με τροφοδοσία 0.8V ενώ το κέρδος έχει εύρος μεταβολής 17dB και μπορεί να ενσωματωθεί σε βρόχο αυτομάτου ελέγχου κέρδους χαμηλής τροφοδοσίας. Για το σκοπό αυτό σχεδιάστηκαν με την τεχνική οδήγησης τρανζίστορ από το υπόστρωμα και δυο κυκλώματα τετραγωνικής συνάρτησης με τροφοδοσία 0.8V και 0.5V αντίστοιχα. / In recent years the need for analog integrated circuits with low-voltage and low-power is more than urgent. The main reason for this need is the rapid growth of portable electronic devices for multimedia applications (laptops, netbooks, mobiles, etc.) and even more for biomedical devices applications. In many cases, these electronic devices provide connectivity to wireless networks (WLANs) and therefore they incorporate transceiver systems. Thus, requirements such as low-voltage and low-power are a necessity. One of the basic analog “building blocks” for circuit design is differential voltage amplifiers. This thesis presents complete solutions for low-voltage differential amplifiers in standard CMOS technology of 0.35μm and 0.18μm. The proposed amplifiers were designed with bulk-driven technique. In the first place are designed differential voltage amplifiers that include input stage with negative resistance circuitry. This way the proposed amplifiers improve the small input transconductance due to bulk-driven transistors. Thus, novel amplifier structures are obtained with a voltage supply equal even to 0.8V. The amplifiers performance is characterized both through simulation and experimental results. The convergence of simulation and experimental results demonstrate that the proposed amplifiers circuits designed with bulk-driven technique are significant solution in the design of low-voltage amplifiers. In the next step a differential bulk-driven voltage follower is designed with 1V voltage supply. The proposed follower is used as a differential input stage for a differential voltage amplifier with the same voltage supply. The proposed amplifier is capable to operate rail-to-rail for common mode input signals. Also, the proposed voltage follower is modified in order to operate in extreme voltage supply of 0.5V. The modified voltage follower is used, again, as a differential input stage for a differential voltage amplifier while the whole amplifier used a voltage supply equal to 0.5V. Both proposed amplifiers topologies that use bulk-driven differential voltage followers as input stages are complete solutions for low-voltage and ultra low-voltage amplifiers applications. Finally, a new technique for linear transconductance variation, applicable in any kind of transconductor, is introduced. The proposed technique is used to build a bulk-driven variable gain amplifier (VGA). The proposed VGA operate with 0.8V voltage supply while produce a gain range variation equal to 17dB. The amplifier could incorporate in an automatic gain control loop (AGC) for low-voltage applications. For this purpose, two bulk-driven voltage squarers circuits with voltage supply 0.8V and 0.5V was also proposed.

Les circuits Smart Power, utilisés dans l’industrie automobile, se caractérisent par l’intégration sur une puce des parties de puissance avec des parties analogiques&numériques basse tension. Leur principal point faible vient de la commutation des structures de puissance sur des charges inductives. Celles-ci injectent des courants parasites dans le substrat, pouvant activer des structures bipolaires parasites inhérentes au layout du circuit, menant à une défaillance ou la destruction du circuit intégré.Ces structures parasites ne sont pas actuellement modélisées dans les outils CAO ni simulées par les simulateurs de type SPICE. L'extraction de ces structures à partir du layout et leur intégration dans les outils CAO est l’objectif du projet européen AUTOMICS, dans le cadre duquel cette thèse a été réalisée.La caractérisation du couplage substrat sur deux cas d’études a permis de valider les modèles théoriques et de les comparer aux simulations utilisant le nouveau modèle de couplage substrat. / Smart Power circuits, used in the automotive industry, are characterized by the integration on one chip of the power parts with low voltage analog and digital parts. Their main weak point comes from the switching of power structures on inductive loads. These inject parasitic currents in the substrate, capable of activating the bipolar parasitic structures inherent in the layout of the circuit, leading to failure or destruction of the integrated circuit.These parasitic structures are not currently integrated into CAD tools nor simulated by SPICE simulators. The extraction of these structures from the layout and their integration into the CAD tools is the objective of the European AUTOMICS project, in which this thesis is carried out.The characterization of the substrate coupling of 2 case study was used to validate theoretical models and compare them to simulations using the new substrate coupling model.

SiC in Space is one of the experiments on KTH’s miniature satellite, MIST. The experiment carries out tests on bipolar junction transistors of silicon and silicon carbide. This thesis describes how the characteristics of a transistor can be measured using analog circuits. The presented circuit design will work as a prototype for the SiC in Space experiment. The prototype measures the base current, the collector current, the base-emitter voltage as well as the temperature of the transistor. This thesis describes how a test circuit may be designed. The selected design has been constructed in incremental steps, with each design choice explained. Different designs have been developed. The designs have been verified with simulations. We have also constructed and tested three different prototypes on breadboards and printed circuit boards. / SiC in Space är ett av experimenten på KTHs miniatyrsatellit, MIST. Experimentet utför test på bipolära transistorer av kisel och kiselkarbid. Detta examensarbete förklarar hur transistorns karakteristik kan mätas med analoga kretsar. Den framtagna kretsdesignen kommer att fungera som en prototyp till SiC in Space-experimentet. Prototypen mäter basströmmen, kollektorströmmen, bas-emitter-spänningen samt temperaturen för transistorn. Detta examensarbete förklarar hur en testkrets kan designas. Den valda designen byggs i inkrementella steg, där varje designval förklaras. Olika designer har utvecklats. Designerna har verifierats genom simuleringar. Vi har också konstruerat och testat tre olika prototyper på kopplingsdäck och kretskort.

<p>To facilitate indoor air quality (IAQ) monitoring, the research described herein develops and implements methods for the electronic integration of two types of gas sensor, each functionalized with a polymer blend tailored for CO₂ detection. A highly sensitive and tunable electronic chemiresistive sensor interface was developed and experimentally validated. This device achieved analog-to-digital conversion (ADC) through a pulse width modulated (PWM) signal, temporary data storage with an efficient data buffering system, and noise reduction and signal amplification utilizing an instrumentation amplifier integrator circuit. These techniques can used beyond CO₂-specific applications to compensate for certain undesirable chemiresistive sensor characteristics, such as low response magnitude and signal noise. Additionally, resonant mass sensing circuitry was combined with an on-chip field programmable gate array (FPGA) implemented frequency counter. Hz-level resolution was achieved with an Alorium Snō FPGA board and a Verilog data acquisition and communication program. This device can monitor up to 16 sensor channels simultaneously and has a straightforward interface with a controllable output. Furthermore, the functionality of each integrated sensor was experimentally validated. With additional work, these integrated designs have the potential to be inexpensive, low-power, highly sensitive devices that are suitable for practical use in IAQ monitoring applications.</p>

<p>Most work on amplifier linearity has focused on the transconductance (gm) linearity, but there is increasing evidence that the voltage-dependence of the gate-source capacitance (Cgs) plays an important role in the linearity of emerging devices. This work addresses the capacitance contribution by incorporating the nonlinearities attributed to the voltage dependency of Cgs of a general FET on a circuit-level Cg amplifier model.</p> <p>An amplifier model including a voltage-dependent Cgs, and a voltage-dependent gm is studied using harmonic analysis and Volterra series. A closed form expression for the  third-order intercept point (IP3) of the amplifier, which depends on the nonlinear coefficients of Cgs, is obtained. A simple design rule, and a formula for the reduction of the IP3 due to the voltage-dependent Cgs are also presented. </p> <p>As application examples, the linearity of an amplifier based on a specific device is analyzed for two cases by extracting the nonlinear circuit parameters of the device. First for an analytic model of a bulk mosfet. Second for a one-dimensional, ballistic, coaxially gated Si nanowire. For low frequencies of design, the distortion introduced by gm is predominant, but for high frequencies it is obscured by the distortion coming from Cgs.</p> <p>We conclude that taking into account the voltage-dependence of Cgs is crucial when predicting the linearity behavior of a Cg amplifier, either designed for high-frequency operation, or based on a device operating near the quantum capacitance limit. </p>

<p>Neuromorphic computing endeavors to develop computational systems capable of emulating the brain’s capacity to execute intricate tasks concurrently and with remarkable energy efficiency. By utilizing new bioinspired computing architectures, these systems have the potential to revolutionize high-performance computing and enable local, low-energy computing for sensors and robots. Organic and soft materials are particularly attractive for neuromorphic computing as they offer biocompatibility, low-energy switching, and excellent tunability at a relatively low cost. Additionally, organic materials provide physical flexibility, large-area fabrication, and printability.</p><p>This doctoral dissertation showcases the research conducted in fabricating a comprehensive spiking organic neuron, which serves as the fundamental constituent of a circuit system for neuromorphic computing. The major contribution of this dissertation is the development of the organic, flexible neuron composed of spiking synapses and somas utilizing ultra-low voltage organic field-effect transistors (OFETs) for information processing. The synaptic and somatic circuits are implemented using physically flexible and biocompatible organic electronics necessary to realize the Polymer Neuromorphic Circuitry. An Axon-Hillock (AH) somatic circuit was fabricated and analyzed, followed by the adaptation of a log-domain integrator (LDI) synaptic circuit and the fabrication and analysis of a differential-pair integrator (DPI). Finally, a spiking organic neuron was formed by combining two LDI synaptic circuits and one AH synaptic circuit, and its characteristics were thoroughly examined. This is the first demonstration of the fabrication of an entire neuron using solid-state organic materials over a flexible substrate with integrated complementary OFETs and capacitors.</p>

<p dir="ltr">The proliferation of internet-connected embedded devices in contemporary computing environments has raised significant concerns regarding data security and confidentiality. Most embedded devices rely on computationally secure cryptographic algorithms to address these imperatives. However, despite the mathematical assurances, the physical implementation of these algorithms introduces vulnerabilities. Specifically, side-channel analysis (SCA) attacks exploit information leakage through various channels, including power consumption, electromagnetic (EM) radiation, timing, cache hits and misses, and other observable characteristics. </p><p dir="ltr">Previous research has introduced the concept of attenuating information-sensitive signatures using an analog cascoded current source for power delivery, coupled with an analog biased PMOS-based local negative feedback mechanism to stabilize the internal node. While this approach achieves robust signature suppression, resulting in higher minimum traces to disclosure (MTD) and enhanced security, it remains limited by its analog nature, making it less adaptable across different technology nodes. This thesis proposes a digital-friendly signature suppression technique that employs a digital cascoded current source and leverages a Ring-oscillator-based bleed path. These digital countermeasures can be further enhanced through time-domain obfuscation techniques. Our work demonstrates a state-of-the-art MTD of 1.25 billion traces for an AES-256 implementation. However, these countermeasures lack provable security guarantees, so continuous stress testing is essential for widespread deployment. Different intelligent attacks can be exploited on these physical countermeasures. Notably, this thesis also presents an intelligent attack on signature attenuation-based physical countermeasures and introduces an attack detector. Developing an intelligent attack detector is an integral part of the commercial adoption of physical countermeasures. </p><p dir="ltr">Next, generic physical countermeasures are often deployed in the $V_{DD}$ port as power side channel analysis is carried out through the $V_{DD}$ port. However, any digital circuit has two standard ports, namely $V_{DD}$ and clock port, and countermeasure through the clock port is mainly unexplored except for the system-level clock randomization technique. Even the clock-randomization technique is rendered ineffective in the presence of post-processing techniques. This thesis introduces a side channel resilience technique by introducing a larger slew at the clock, thereby improving MTD by $100\times$.</p><p dir="ltr">Next, these physical countermeasures do not come with any provable security guarantee. Hence, it is important to stress-test the countermeasures. This thesis does so and finds an exploitable point to reduce MTD by 1000$\times$. An attack detector of such an attack is also proposed.</p><p dir="ltr">Further, an attack detection strategy against side-channel analysis (SCA) or fault injection attacks (FIA) is also required. A detection and mitigation approach often gives us the option of duty-cycled countermeasures, hence reducing the energy overhead. This thesis proposes and analyzes a self-aware inductive loop-based attack detection strategy to detect SCA and FIA and enhance the signature attenuation countermeasures. </p><p dir="ltr">Finally, we explore opportunities for integrating these lightweight generic techniques into recently standardized Post-Quantum Cryptographic (PQC) cores. Specifically, we present an optimized implementation of the Saber PQC core, a NIST standardization finalist, achieving the lowest area and energy consumption. Future work could involve deploying lightweight PQC cores with synthesizable physical countermeasures to enhance security against quantum algorithms and physical side-channel attacks.</p>

Rail à rail entrée - sortie, classe AB, faible consommation sont autant de critères que le concepteur d'amplificateur opérationnel (AOP) intègre pour réaliser une cellule analogique performante. Pour un AOP standard, l'accent n'est pas porté sur une caractéristique particulière mais sur l’ensemble de celle-ci. Dans le but d'augmenter le nombre de fonction par circuit intégré, la tension d'alimentation des AOPs ainsi que leur consommation en courant tendent à diminuer. L'objectif des circuits réalisés est de doubler le facteur de mérite des circuits déjà présents dans le portefeuille de STMicroelectronics. Le facteur de mérite est un indice qui compare des circuits équivalents. Il est défini par le rapport entre le produit capacité de charge x produit gain bande-passante et le produit courant de consommation x tension d'alimentation. L'état de l'art des structures d'AOPs a orienté l'étude vers des structures analogiques possédant au moins trois étages de gain. Un niveau de gain statique supérieur à la centaine de décibel est nécessaire pour utiliser ces amplificateurs dans des systèmes contre-réactionnés. Puisque chaque étage de gain introduit un noeud haute impédance et que chaque noeud haute impédance est à l'origine d'un pôle, l'étude de la compensation fréquentielle s'est avérée indispensable pour obtenir des structures optimisées. Pour simplifier l'étude de ces AOPs, le développement d'outils d'aide à la conception analogique a contribué à l'automatisation de plusieurs tâches.. Ces différents travaux ont été ponctués par la réalisation et la caractérisation de six circuits. Les compensations fréquentielles utilisées dans ces circuits sont la compensation nested miller , la compensation reversed nested miller et la compensation multipath nested miller . Parmi les six circuits, une moitié a été réalisée uniquement dans le but de valider des concepts de compensation fréquentielle et l'autre moitié avec toutes les contraintes d'une documentation technique propre à la famille d'AOP standard. / To be in line with the standard of operational amplifier (opamp), designer integrates in his circuit several functionalities like a Rail to rail input and output, class AB output stage and low power consumption. For standard products, there is no outstanding performance but the average of all of them has to be good. In order to increase the number of functions on an integrated circuit, the power supply and current consumption are permanently decreasing. The aim of the designed circuits is to double the figure of merit (FOM) of the actual ST portfolio products. The FOM allows the comparison of similar opamps. It is defined by the ratio of the product of capacitive load x gain-bandwith product over the power consumption. The opamps’ state of the art has led this study to three stages analog cells. A DC gain higher than hundreds of decibel is required to use opamps in feedback configuration. As each stage of the structure introduces a high impedance node and as each high impedance node introduces a pole, the study of frequency compensation technics became essential for well optimized structures. To simplify the study of the opamps, three tools have been developed to help in the design of the frequency compensation network and to automate some tasks. This work has been followed by the realization of six cells. Three of them were designed to validate frequency compensation structure and the other three to satisfy a standard opamp datasheet. Nested Miller, Reversed Nested Miller and Multipath Nested Miller compensations were used in these circuits.

<p>The last few decades have witnessed unprecedented growth in multiple areas of electronics spanning low-power sensing, intelligent computing and high-speed wireless connectivity. In the foreseeable future, there would be hundreds of billions of computing devices, sensors, things and people, wherein the technology will become intertwined with our lives through continuous interaction and collaboration between humans and machines. Such human-centric ideas give rise to the concept of internet of bodies (IoB), which calls for novel and energy-efficient techniques for sensing, processing and secure communication for resource-constrained IoB nodes.As we have painfully learnt during the pandemic, point-of-care diagnostics along with continuous sensing and long-term connectivity has become one of the major requirements in the healthcare industry, further emphasizing the need for energy-efficiency and security in the resource-constrained devices around us.</p> <p>  </p> <p>  With this vision in mind, I’ll divide this dissertation into the following chapters. The first part (Chapter 2) will cover time-domain sensing techniques which allow inherent energy-resolution scalability, and will show the fundamental limits of achievable resolution. Implementations will include 1) a radiation sensing system for occupational dosimetry in healthcare and mining applications, which can achieve 12-18 bit resolution with 0.01-1 µJ energy dissipation, and 2) an ADC-less neural signal acquisition system with direct Analog to Time Conversion at 13pJ/Sample. The second part (Chapters 3 and 4) of this dissertation will involve the fundamentals of developing secure energy-efficient electro-quasistatic (EQS) communication techniques for IoB wearables as well as implants, and will demonstrate  2 examples: 1) Adiabatic Switching for breaking the αCV^2f limit of power consumption in capacitive voltage mode human-body communication (HBC), and 2) Bi-Phasic Quasistatic Brain Communication (BP-QBC) for fully wireless data transfer from a sub-6mm^3, 2 µW brain implant. A custom modulation scheme, along with adiabatic communication enables wireline-like energy efficiencies (<5pJ/b) in HBC-based wireless systems, while the BP-QBC node, being fully electrical in nature, demonstrates sub-50pJ/b efficiencies by eliminating DC power consumption, and by avoiding the transduction losses observed in competing technologies, involving optical, ultrasound and magneto-electric modalities. Next in Chapter 5, we will show an implementation of a reconfigurable system that would include 1) a human-body communication transceiver and 2) a traditional wireless (MedRadio) transceiver on the same integrated circuit (IC), and would demonstrate methods to switch between the two modes by detecting the placement of the transmitter and receiver devices (on-body/away from the body). Finally, in Chapter 6, we shall show a technique of augmenting security in resource-constrained devices through authentication using the Analog/RF properties of the transmitter, which are usually discarded as non-idealities in a digital transceiver chain. This method does not require any additional hardware in the transmitter, making it an extremely promising technique to augment security in highly resource-constrained scenarios. Such energy-efficient intelligent sensing and secure communication techniques, when combined with intelligent in-sensor-analytics at the resource-constrained nodes, can potentially pave the way for perpetual, and even batteryless systems for next-generation IoT, IoB and healthcare applications.</p>

<p>The "Maker Movement" is a cultural phenomena rooted in DIY culture, which stresses making devices and creations on your own rather than purchasing it ready-made. At the core of the Maker Movement, is the "Maker Mindset"; a collection of attitudes, beliefs and behaviors that emphasize the importance of creativity, experimentation and innovation in the learning process. Since the Maker Mindset embodies constructionist principles at its core that push makers to experiment and problem-solve by collaborating with fellow makers through hands-on activities, it can be said that these activities comprise of Creative, Learning and Collaborative experiences. While Internet-of-Things devices have long been used to enhance these activities, research pertaining to using Augmented Reality in tandem with IoT for the purpose of enhancing experiences core to the Maker Mindset is relatively unexplored. Three different systems were developed with the goal of addressing this -- MicrokARts, ShARed IoT and MechARspace. Each system focuses on enhancing one of the three core experiences through AR-compatible IoT devices, whilst ensuring that they do not require prerequisite knowledge in order to author AR experiences. These systems were evaluated through user studies and testing over a variety of age-groups, with each system successfully enhancing one core experience each through the use of AR-IoT interactions.</p>