Electronic components, based on current semiconductor technologies and operating in radiation rich environments, suffer degradation of their performance as a result of radiation exposure. Silicon carbide (SiC) provides an alternate solution as a radiation hard material, because of its wide bandgap and higher atomic displacement energies, for devices intended for radiation environment applications. However, the radiation tolerance and reliability of SiC-based devices needs to be understood by testing devices  under controlled radiation environments. These kinds of studies have been previously performed on diodes and MESFETs, but multilayer devices such as bipolar junction transistors (BJT) have not yet been studied. In this thesis, SiC material, BJTs fabricated from SiC, and various dielectrics for SiC passivation are studied by exposure to high energy ion beams with selected energies and fluences. The studies reveal that the implantation induced crystal damage in SiC material can be partly recovered at relatively low temperatures, for damag elevels much lower than needed for amorphization. The implantation experiments performed on BJTs in the bulk of devices show that the degradation in deviceperformance produced by low dose ion implantations can be recovered at 420 oC, however, higher doses produce more resistant damage. Ion induced damage at the interface of passivation layer and SiC in BJT has also been examined in this thesis. It is found that damaging of the interface by ionizing radiation reduces the current gain as well. However, for this type of damage, annealing at low temperatures further reduces the gain. Silicon dioxide (SiO2) is today the dielectric material most often used for gate dielectric or passivation layers, also for SiC. However, in this thesis several alternate passivation materials are investigated, such as, AlN, Al2O3 and Ta2O5. These materials are deposited by atomic layer deposition (ALD) both as single layers and in stacks, combining several different layers. Al2O3 is further investigated with respect to thermalstability and radiation hardness. It is observed that high temperature treatment of Al2O3 can substantially improve the performance of the dielectric film. A radiation hardness study furthermore reveals that Al2O3 is more resistant to ionizing radiation than currently used SiO2 and it is a suitable candidate for devices in radiation rich applications. / QC 20120117

Advances in space and nuclear technologies are limited by the capabilities of the conventional silicon (Si) electronics. Hence, there is a need to explore materials beyond Si with enhanced properties to operate in extreme environments. In this regards, silicon carbide (4H-SiC), a wide bandgap semiconductor, provides suitable solutions. In this thesis, radiation effects of 4H-SiC bipolar devices, circuits and dielectrics for SiC are investigated under various radiation types. We have demonstrated for the first time the radiation hardness of 4H-SiC logic circuits exposed to extremely high doses (332 Mrad) of gamma radiation and protons. Comparisons with previously available literature show that our 4H-SiC bipolar junction transistor (BJT) is 2 orders of magnitude more tolerant under gamma radiation to existing Si-technology. 4H-SiC devices and circuits irradiated with 3 MeV protons show about one order of magnitude higher tolerance in comparison to Si. Numerical simulations of the device showed that the ionization is most influential in the degradation process by introducing interface states and oxide charges that lower the current gain. Due to the gain reduction of the BJT, the voltage reference of the logic circuit has been affected and this, in turn, degrades the voltage transfer characteristics of the OR-NOR gates. One of the key advantages of 4H-SiC over other wide bandgap materials is the possibility to thermally grow silicon oxide (SiO2) and process device in line with advanced silicon technology. However, there are still questions about the reliability of SiC/SiO2 interface under high power, high temperature and radiation rich environments. In this regard, aluminium oxide (Al2O3), a chemically and thermally stable dielectric, has been investigated. It has been shown that the surface cleaning treatment prior to deposition of a dielectric layer together with the post dielectric annealing has a crucial effect on interface and oxide quality. We have demonstrated a new method to evaluate the interface between dielectric/4H-SiC utilizing an optical free carrier absorption technique to quantitative measure the charge carrier trapping dynamics. The radiation hardness of Al2O3/4H-SiC is demonstrated and the data suggests that Al2O3 is better choice of dielectric for devices in radiation rich applications. / <p>QC 20170119</p>

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第21772号 / 工博第4589号 / 新制||工||1715(附属図書館) / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 藤田 静雄, 准教授 杉山 和彦 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DFAM

Abstract Although avalanche switching has been known since the 1950s, a trustworthy one-dimensional physical interpretation of the practically interesting high-current mode ("secondary breakdown") in a Si avalanche transistor has appeared only within the last decade and thanks to numerical one-dimensional and two-dimensional physics-based device modelling. A good fit with experimental waveforms has been achieved only for high-current, long-duration pulses (~100&#160;A/7 ns), however, and modelling fails in the case of shorter pulses in a range that is of greater practical importance. One significant finding in this thesis is that reliable modelling of a Si avalanche transistor is in general impossible without taking account of three-dimensional effects. The task is a challenging one, as it is being put forward for the first time and state-of-the-art simulators are unable to model three-dimensional avalanche dynamics with an external circuit included (i.e. in “MixedMode”). Thus a smart approach was adopted which allowed the main features of the three-dimensional transient to be explained using a two-dimensional simulator and compared with the experimental data. The focus was on a trade-off of between high switching efficiency in an avalanche transistor (high-speed switching with a lower residual voltage as occurs at extremely high current densities) and device reliability as determined by local overheating during a single pulse, similarly resulting from high current density. This denotes the practical importance of the work performed here, as the current density is directly affected by three-dimensional dynamic processes. The second task performed in this thesis concerns the reliability of the GaAs avalanche transistors developed recently in the Electronics Laboratory and demonstrated of unique (superfast) switching and high-power-density sub-THz emission for mm-wave imaging and radars. Critically important for this new device is the limitation originating from premature breakdown at the surface of the GaAs p-n junction with a high density of surface states. Two of the results of this work are also fairly challenging: (i) the mechanism of "soft" surface breakdown intrinsic to all GaAs transistor mesas was interpreted in terms of the surface trapping of avalanche-generated electrons as suggested here, and (ii) passivation of the surface with a chalcogenide glass was suggested, as this allows the premature surface breakdown to be suppressed completely, an effect that has proved to be caused by a large negative surface charge formed on the “U centres” intrinsic to a chalcogenide glass. / Tiivistelmä Vaikka avalanche läpilyönti pii-transistoreissa on tunnettu jo 1950-luvulta lähtien, luotettava 1-dimensionaalinen fysikaalinen tulkinta ilmiöstä käytännön sovellusten kannalta kiinnostavilla suurilla virtatasoilla (ns. “secondary breakdown”) on esitetty vasta viime vuosikymmenen aikana 1- ja 2-dimensionaalisiin numeerisiin simulointeihin ja fysikaaliseen mallinnukseen perustuen. Kokeellisten mittausten ja simulointien välille on saatu hyvä sovitus kuitenkin vain sellaisessa ohjaustilanteessa, jossa transistori toimii suurella virtatasolla ja tuottaa leveitä virtapulsseja (~100&#160; A / 7 ns); mallinnus ei vastaa mittaustuloksia lyhyillä virtapulsseilla, jotka kuitenkin ovat tärkeitä käytännön sovellusten kannalta. Yksi tämän työn keskeisiä havaintoja on se, että piipohjaisen avalanche transistorin luotettava mallintaminen ei ole käytännössä yleisesti mahdollista ottamatta huomioon 3-dimensionaalisia (3D) efektejä. Tällainen mallinnus, jota tässä työssä on kehitetty ensimmäistä kertaa, on vaikeaa, koska kaupalliset simulointiohjelmistot eivät kykene käsittelemään avalanche ilmiön dynamiikka 3-dimensionaalisesti tilanteessa, jossa transistoriin on kytketty ulkoinen piiri (ns. mixed-mode -simulointitilanne). Tähän kehitettiin tekniikka, joka mahdollistaa 3-dimensionaalisen kytkentätransientin tärkeimpien piirteiden selittämisen ja mittaustuloksiin vertaamisen 2-dimensionaalisten simulointien perusteella. Erityisesti pyrittiin selvittämään avalanche transistorin korkean kytkentähyötysuhteen (kollektori-emitterin ns. residual-jännitteen käyttäytyminen virrantiheystason mukaan) ja komponentin luotettavuuden välistä riippuvuutta. Luotettavuuteen vaikuttaa olennaisesti komponentin sisäinen, lokalisoitunut lämpötilamaksimi, joka myös riippuu keskeisesti komponentin virrantiheystasosta kytkentäpulssin aikana. Toisaalta virrantiheyteen vaikuttavat juuri komponentin 3-dimensionaaliset dynaamiset prosessit, joten työn käytännöllinen merkitys on suuri. Työn toisen osa käsittelee elektroniikan laboratoriossa äskettäin kehitetyn GaAs-avalanche transistorin luotettavuutta. Tällaisella transistorilla on demonstroitu olevan erityislaatuinen supernopea kytkeytymisefekti, ja se emittoi korkealla tehotasolla sähkömagneettista säteilyä n. 0,1–1 THz taajuusalueella. GaAs-avalanche transistoria voidaan täten potentiaalisesti hyödyntää mm-alueen kuvantamisessa ja tutkissa. Tämän uuden transistorin luotettavuuteen vaikuttaa ratkaisevasti rajoitus, joka aiheutuu ennenaikaisen, GaAs-pn-liitoksen pinnassa vaikuttavasta suuresta pintatilatiheydestä johtuvan läpilyönnin mahdollisuudesta. Työn kaksi keskeistä tulosta ovat: (i) kaikilla GaAs-transistoreilla ilmenevä ns. ”pehmeä”-läpilyönti aiheutuu avalanche ilmiön synnyttämien elektronien loukkuuntumisesta pinta-tiloihin, ja (ii) pinnan passivointi kalkopyriittilasilla estää läpilyönnin kokonaan, koska kalkopyriittilasille luonteenomaiset ”U-tilat” aiheuttavat liitoksen pintaan korkean negatiivisen pintavarauksen.

Orientador: Peter Jurgen Tatsch / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-15T23:27:09Z (GMT). No. of bitstreams: 1 Manera_LeandroTiago_D.pdf: 3739799 bytes, checksum: 12a6fc4ebbea20e529e4e7e2c7c5a761 (MD5) Previous issue date: 2010 / Resumo: Este trabalho teve como objetivo a montagem de um sistema de caracterização de ruído de alta e de baixa freqüência, utilizando equipamentos disponíveis no Centro de Componentes Semicondutores da Unicamp. Foi montado um sistema para a caracterização do ruído de baixa freqüência em dispositivos semicondutores e desenvolveu-se um método para a análise da qualidade de interfaces e cálculo de cargas, utilizando o ruído 1/f. Na descrição do ruído em baixa freqüência é apresentado em detalhes todo o arranjo utilizado para a medição, além dos resultados da medida em transistores nMOS e CMOS do tipo p e do tipo n fabricados no Centro. Detalhes importantes sobre o cuidado com a medição, tais como a utilização de baterias para a alimentação dos dispositivos e o correto aterramento, também são esclarecidos. A faixa de freqüência utilizada vai de 1 Hz até 100 KHz. Como aplicação, a medida de ruído é utilizada como ferramenta de diagnóstico de dispositivos semicondutores. Resultados destas medidas também são apresentados. Foi desenvolvido também um sistema para a medição do ruído em alta freqüência. A caracterização teve como objetivo determinar o parâmetro conhecido como Figura de Ruído. Apresenta-se além da descrição do arranjo utilizado na medição, os equipamentos e a metodologia empregada. Em conjunto com as medidas de ruído também são apresentados os resultados das medidas de parâmetros de espalhamento. Para a validação do método de obtenção desse conjunto de medidas, um modelo de pequenos sinais de um transistor HBT, incluindo as fontes de ruído é proposto, e é apresentado o resultado entre a medição e a simulação. A faixa disponível para medida vai de 45 MHz até 30 GHz para os parâmetros de espalhamento e de 10 MHz até 1.6 GHz para medida de figura de ruído / Abstract: The main goal of this work is the development of a noise characterization system for high and low frequency measurements using equipments available at the Center for Semiconductor Components at Unicamp. A low noise characterization system for semiconductors was built and by means of 1/f noise measurement it was possible to investigate semiconductor interface condition and oxide traps density. Detailed information about the test set-up is presented along with noise measurement data for nMOS, p and n type CMOS transistors. There is also valuable information to careful conduct noise measurements, as using battery powered devices and accurate grounding procedures. The low noise set-up frequency range is from 1 Hz up to 100 KHz. Noise as a diagnostic tool for quality and reliability of semiconductor devices is also presented. Measurement data is also shown. A measurement set-up for high frequency noise characterization was developed. Measurements were carried out in order to determine the noise figure parameter (NF) of the HBT devices. Comprehensive information about the test set-up and equipments are provided. Noise data measurements and s-parameters are also presented. In order to validate the measurement procedure, a small signal model for HBT transistor including noise sources is presented. Comparisons between simulation and measured data are performed. The s-parameters frequency range is from 45 MHz to 30 GHz, and noise set-up frequency range is from 10 MHz up to 1.6 GHz / Doutorado / Eletrônica, Microeletrônica e Optoeletrônica / Doutor em Engenharia Elétrica

SiC in Space is one of the experiments on KTH’s miniature satellite, MIST. The experiment carries out tests on bipolar junction transistors of silicon and silicon carbide. This thesis describes how the characteristics of a transistor can be measured using analog circuits. The presented circuit design will work as a prototype for the SiC in Space experiment. The prototype measures the base current, the collector current, the base-emitter voltage as well as the temperature of the transistor. This thesis describes how a test circuit may be designed. The selected design has been constructed in incremental steps, with each design choice explained. Different designs have been developed. The designs have been verified with simulations. We have also constructed and tested three different prototypes on breadboards and printed circuit boards. / SiC in Space är ett av experimenten på KTHs miniatyrsatellit, MIST. Experimentet utför test på bipolära transistorer av kisel och kiselkarbid. Detta examensarbete förklarar hur transistorns karakteristik kan mätas med analoga kretsar. Den framtagna kretsdesignen kommer att fungera som en prototyp till SiC in Space-experimentet. Prototypen mäter basströmmen, kollektorströmmen, bas-emitter-spänningen samt temperaturen för transistorn. Detta examensarbete förklarar hur en testkrets kan designas. Den valda designen byggs i inkrementella steg, där varje designval förklaras. Olika designer har utvecklats. Designerna har verifierats genom simuleringar. Vi har också konstruerat och testat tre olika prototyper på kopplingsdäck och kretskort.