Voltage-dependent channels on the dendrites of motoneurons provide additional current that amplifies or dampens synaptic current en route to the soma. The specific consequences will depend on the density and distribution of the voltage-dependent channels. HCN channels generate a positive inward current in response to hyperpolarization. HCN channels are responsible for a resonance phenomenon in motoneurons where inputs of certain frequencies are preferentially amplified. Modelling studies indicate that this resonance behaviour only occurs if HCN channels are uniformly distributed on the dendritic tree. However, the distribution of HCN channels on the dendrites of motoneurons is unknown. Furthermore, current techniques for measuring channel density on dendrites suffer from methodological limitations that prevent sampling on a scale necessary to map the distribution of voltage-dependent channels across the dendritic tree. The goal of the present study is to develop a high throughput method for measuring the membrane-associated density of voltage-dependent channels using immunohistochemical, confocal and three-dimensional image analysis techniques. Secondly, the proximal to distal distribution of membrane-associated channels formed by the HCN1-subunit on the dendritic trees of trapezius motoneurons in the adult feline will be compared. Antidromically identified motoneurons innervating the trapezius muscle were intracellularly stained in order to visualize the entire dendritic tree. HCN1-subunit containing channels were labeled with a specific antibody. Dendritic segments (n=27 to 92) of ten trapezius motoneurons at different distances from the soma were acquired using confocal microscopy and rendered into a three-dimensional volume. The perimeter of the intracellular stain was used to define the membrane-cytoplasmic border. Analysis of the HCN1 immunoreactivitywas constrained to this perimeter. This technique provides a means of extracting membrane-associated HCN1 labeling and therefore the functional distribution of HCN1 channels. The density of membrane-associated HCN1 immunoreactvity across the dendritic tree was either uniform or increased with distance from the soma among the ten trapezius motoneurons. The increase in HCN1 density with distance from the soma was inversely related to the density of HCN1 on the soma and proximal dendrites. Lastly, the change in HCN1 density with distance from the soma was inversely related to the total input conductance of the motoneuron. / Thesis (Master, Neuroscience Studies) -- Queen's University, 2012-08-01 13:59:32.403

As correntes subliminares determinam propriedades da membrana neuronal, tais como a resistência de entrada (Rin) e a constante de tempo (tm). Nesta tese, estudamos mecanismos pelos quais duas correntes subliminares (corrente ativada por hiperpolarização, Ih, e corrente de sódio persistente, INaP) determinam Rin e tm em dois tipos de neurônio: neurônio fusiforme do núcleo coclear dorsal e célula piramidal da região CA1 do hipocampo. A tese está dividida em três partes: a primeira estuda como a Ih atua concomitantemente com a corrente de potássio retificadora de entrada (IKIR) para manter Rin estacionária entre neurônios fusiformes com heterogeneidade de disparo (silenciosos, sem disparos espontâneos, e ativos, com disparos espontâneos regulares). Na segunda parte, usa-se uma combinação de modelagem computacional com a técnica experimental de dynamic-clamp em neurônios piramidais de fatias hipocampais para mostrar que a criação de uma região de inclinação negativa na curva I/V (condutância de inclinação negativa) pela ativação rápida da INaP é responsável pelo aumento de Rin e tm e pela amplificação e prolongamento dos potenciais pós-sinápticos das células. Finalmente, a terceira parte estabelece o mecanismo pelo qual a INaP e Ih controlam a tm da célula. Para isso, propomos um novo conceito denominado \"condutância de inclinação dinâmica\" que leva em consideração a cinética das correntes e explica os efeitos observados das cinéticas de Ih e INaP sobre tm. Com base nos resultados, prevemos que uma Ih com cinética rápida atenua e encurta os potenciais pós-sinápticos excitatórios muito mais que uma Ih com cinética lenta. / Subthreshold currents determine the neuronal membrane properties, such as the input resistance (Rin) and the membrane time constant (tm). In this thesis, we studied the mechanisms by which two subthreshold currents (the hyperpolarization-activated current, Ih, and the persistent sodium current, INaP) determine Rin and tm in two types of neurons: the fusiform neuron of the dorsal cochlear nucleus and the pyramidal cell of the CA1 region of the hippocampus. The thesis is divided in three parts: the first part studies how Ih acts concomitantly with the inwardly rectifying potassium current (IKIR) to equalize Rin among fusiform neurons with firing heterogeneity (quiet, without spontaneous firing and active, with regular spontaneous firing). In the second part, we used a combination of computational modeling with the experimental technique dynamic-clamp in pyramidal cells of hippocampal slices to show that the creation of a negative slope region in the I/V curve (negative slope conductance) by the fast activation of the INaP is responsible for the increase of Rin and tm, and for the amplification and prolongation of postsynaptic potentials in these cells. Finally, the third part establishes the mechanism whereby INaP and Ih control tm in the cell. For this, we propose a new concept called \"dynamic slope conductance\", which takes into consideration the current kinetics and explains the observed effects of Ih and INaP kinetics on tm. Based on the results, we predict that an Ih current with fast kinetics attenuates and shortens excitatory postsynaptic potentials strongly than an Ih current with slower kinetics.

The subthreshold region of operation has simple physics which allows for a balanced-force approach to behavioral modeling that has shown to be robust to temperature, and a model that encapsulates MOSFET behavior across all operational regions has been developed. The subthreshold region of operation also allows for injection of charge onto floating nodes that allows for persistent storage that can be used in a variety of applications. The combination of charge storage and device modeling has allowed for the development of programmable circuits for digital applications.

A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate with very low duty cycle due to limited energy. Ideally these sensor networks will be massive in size and dense in order to promote redundancy. In addition the networks will be collectively intelligent and adaptive. To achieve these goals, distributed sensor networks will require very small,inexpensive nodes that run for long periods of time on very little energy. One component of such network nodes is an A/D converter. An ADC acts as a crucial interface between the sensed environment and the sensor network as a whole. The work presented here focuses on moderate resolution, and moderate speed, but ultra-low-power ADCs. The 6 bit current-mode algorithmic pipelined ADC reported here consumes 8 pJ/bit samples at 0.65V supply and 130 kS/s. The current was chosen as the information carrying quantity instead of voltage as it is more favorable for low-voltage and low-power applications. The reference current chosen was 150nA. All the blocks are using transistors operating in subthreshold or weak inversion region of operation, to work in low-voltage and low current supply. The DNL and INL plots are given in simulation results section. The area of the overall ADC was 0.046 mm2 only.

As correntes subliminares determinam propriedades da membrana neuronal, tais como a resistência de entrada (Rin) e a constante de tempo (tm). Nesta tese, estudamos mecanismos pelos quais duas correntes subliminares (corrente ativada por hiperpolarização, Ih, e corrente de sódio persistente, INaP) determinam Rin e tm em dois tipos de neurônio: neurônio fusiforme do núcleo coclear dorsal e célula piramidal da região CA1 do hipocampo. A tese está dividida em três partes: a primeira estuda como a Ih atua concomitantemente com a corrente de potássio retificadora de entrada (IKIR) para manter Rin estacionária entre neurônios fusiformes com heterogeneidade de disparo (silenciosos, sem disparos espontâneos, e ativos, com disparos espontâneos regulares). Na segunda parte, usa-se uma combinação de modelagem computacional com a técnica experimental de dynamic-clamp em neurônios piramidais de fatias hipocampais para mostrar que a criação de uma região de inclinação negativa na curva I/V (condutância de inclinação negativa) pela ativação rápida da INaP é responsável pelo aumento de Rin e tm e pela amplificação e prolongamento dos potenciais pós-sinápticos das células. Finalmente, a terceira parte estabelece o mecanismo pelo qual a INaP e Ih controlam a tm da célula. Para isso, propomos um novo conceito denominado \"condutância de inclinação dinâmica\" que leva em consideração a cinética das correntes e explica os efeitos observados das cinéticas de Ih e INaP sobre tm. Com base nos resultados, prevemos que uma Ih com cinética rápida atenua e encurta os potenciais pós-sinápticos excitatórios muito mais que uma Ih com cinética lenta. / Subthreshold currents determine the neuronal membrane properties, such as the input resistance (Rin) and the membrane time constant (tm). In this thesis, we studied the mechanisms by which two subthreshold currents (the hyperpolarization-activated current, Ih, and the persistent sodium current, INaP) determine Rin and tm in two types of neurons: the fusiform neuron of the dorsal cochlear nucleus and the pyramidal cell of the CA1 region of the hippocampus. The thesis is divided in three parts: the first part studies how Ih acts concomitantly with the inwardly rectifying potassium current (IKIR) to equalize Rin among fusiform neurons with firing heterogeneity (quiet, without spontaneous firing and active, with regular spontaneous firing). In the second part, we used a combination of computational modeling with the experimental technique dynamic-clamp in pyramidal cells of hippocampal slices to show that the creation of a negative slope region in the I/V curve (negative slope conductance) by the fast activation of the INaP is responsible for the increase of Rin and tm, and for the amplification and prolongation of postsynaptic potentials in these cells. Finally, the third part establishes the mechanism whereby INaP and Ih control tm in the cell. For this, we propose a new concept called \"dynamic slope conductance\", which takes into consideration the current kinetics and explains the observed effects of Ih and INaP kinetics on tm. Based on the results, we predict that an Ih current with fast kinetics attenuates and shortens excitatory postsynaptic potentials strongly than an Ih current with slower kinetics.

This design covers the design of an integrated circuit (IC) in support of the active contact lens project at Cal Poly. The project aims to monitor intraocular eye pressure (IOP) to help diagnose and treat glaucoma, which is expected affect 6.3 million Americans by 2050. The IC is designed using IBM’s 130 nm 8RF process, is powered by an on-lens thin film 3.8 V rechargeable battery, and will be fabricated at no cost through MOSIS. The IC features a low-power linear regulator that powers a current-starved voltage-controlled oscillator (CSVCO) used for establishing a backscatter communication link. Additional circuitry is included to regulate power to and from the battery. An undervoltage lockout circuit protects the battery from deep discharge damage. When recharging, a rectifier and a voltage regulator provides overvoltage protection. These circuit blocks are biased primarily using a 696 mV subthreshold voltage reference that consumes 110.5 nA.

This thesis presents techniques to implement analog-to-digital converters (ADCs) under an ultra-low-supply-voltage of 0.2 V to reduce the power consumption. The thesis proposes a dynamic bulk biasing circuit to adjust the PMOS bulk voltage to balance the NMOS and PMOS drain currents to guarantee functionality in the presence of process, voltage, and temperature variations. The dynamic bulk bias circuit is analyzed rigorously to show its functionality. This thesis also describes a new comparator suitable for a 0.2-V supply using ac-coupling, stacked input pairs, and voltage-boosted load capacitor. A 10-bit 5-kS/s successive-approximation-register (SAR) ADC in a 180-nm CMOS process with a supply voltage of 0.2 V demonstrates these ideas. The ADC exhibits a differential nonlinearity (DNL) and integral nonlinearity (INL) within +0.42/-0.45 and +0.62/-0.67 LSB, respectively. The measured SFDR and SNDR at 5 kS/s with a Nyquist-frequency input are 65.9 dB and 52.1 dB, respectively. The entire ADC and dynamic bulk biasing circuitry consume 22 nW including leakage power to yield a figure-of-meirt (FoM) of 8.8 fJ/conv.-step. Measurements of multiple chips show the proposed dynamic bulk biasing fully recovers the ADC performance when the supply voltage is varied. The nW power consumption makes the design well suited for wireless sensor node and energy harvester applications.

Over the past couple decades, the capabilities of battery-powered electronics has expanded dramatically. What started out as large bulky 2-way radios, wristwatches, and simple pacemakers, has evolved into pocket sized smart-phones, digital cameras, person digital assistants, and implantable biomedical chips that can restore hearing and prevent heart attacks. With this increase in complexity comes an increase in the amount of processing, which runs on a limited energy source such as a battery or scavenged energy. It is therefore desirable to make the hardware as energy efficient as possible. Many battery-powered systems require digital signal processing, which often makes up a large portion of the total energy consumption. The digital signal processing of a battery-powered system is therefore a good target for power reduction techniques. One method of reducing the power consumption of digital signal processing is to operate the circuit in the subthreshold region, where the supply voltage is lower than the threshold voltage of the transistors. Subthreshold operation greatly reduces the power and energy consumption, but also decreases the maximum operating frequency. Many digital signal processing applications have real-time throughput requirements, so various architectural level techniques, such as pipelining and parallelism, must be used in order to achieve the required performance. This thesis investigates the use of parallelization and subthreshold operation to lower the power consumption of digital signal processing applications, while still meeting throughput requirements. Using an off the shelf fast fourier transform architecture, it will be shown that through parallelization and subthreshold operation, a 70% reduction in power consumption can be achieved, all while matching the performance of a nominal voltage single core architecture. Even better results can be obtained when an architecture is specifically designed for subthreshold operation. A novel Discrete Wavelet Transform architecture is presented that is designed to eliminate the need for memory banks, and a power reduction of 26x is achieved compared to a reference nominal voltage architecture that uses memory banks. Issues such as serial to parallel data distribution, dynamic throughput scaling, and memory usage are also explored in this thesis. Finally, voltage scaling greatly increases the design space, so power and timing analysis can be very slow due long SPICE simulation times. A simulation framework is presented that can characterize subthreshold circuits accurately using only fast gate level design automation tools. / Master of Science

Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, effective, and comprehensive technique for designers to estimate power and delay of a design operating in the Ultra-Low-Voltage region. While some frameworks and mathematical models exist to estimate power or delay, certain limitations exist, such as being applicable to either power or delay, or within a certain region of transistor operation. This thesis presents a simulation framework that can quickly and accurately characterize a circuit from nominal voltage all the way down into the subthreshold region. The framework uses the nominal frequency and power of a target circuit, which can be obtained using gate-level or transistor-level simulation tools as well as normalized ring oscillator curves to predict delay and power characteristics at lower operating voltages. A specific contribution of this thesis is to introduce a weighted average method, which is a major improvement to a previously published form of this framework. Another contribution is that the amount of process variation in ULV regions of a circuit can be estimated using the proposed framework. The weighted averages framework takes into account the types of gates that are used in the circuit and critical path to give a more accurate power and timing characterization. Despite being many orders of magnitude lower than the nominal voltage, the errors are no greater than 11.27 percent for circuit delay, 16.96 percent for active energy, and 4.86 percent for leakage power for the weighted averages technique. This is in contrast to the original framework which has a maximum error of 39.75, 17.60, and 8.90 percent for circuit delay, active energy, and leakage power, respectively. To validate our framework, a detailed analysis is given in the presence of a variety of design parameters such as fanout, transistor widths, et cetera. In addition, we also validate our framework for a range of sequential benchmark circuits. / Master of Science

I propose compact models of single-gate (SG) and double-gate (DG) JFETs predicting the current-voltage characteristics for both long and short channel devices. In order to make the current equation continuous through all operating conditions from subthreshold to well-above threshold, without non-physical fitting parameters, mobile carriers in depletion region are considered. For describing the short channel behavior, relevant parameters extracted from the two-dimensional analytical solution of Poisson's equation are used for modifying long channel equations. Comparisons of models with the numerical simulation showing close agreement are presented. Based on models, merits of DG JFET over SG JFET and SG MOSFET are discussed by examining the schematic circuit diagram describing the relation between gate and channel potentials for each device. / text