Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

Major depressive disorder (MDD) is a disorder defined by mood disturbance, but the deficits in emotional reactivity that accompany MDD are not yet fully characterized. Researchers have utilized the emotion-modulated startle paradigm to investigate emotional responding among depressed individuals with mixed results. Inconsistent results may be due in part to the heterogeneity of mood disorders, including variation in mood severity. The current study utilized an emotion-modulated startle procedure with 33 individuals currently experiencing a major depressive episode, 25 individuals currently experiencing a minor depressive episode (mD), and 31 healthy controls. Severity of depression, anxiety, and positive and negative mood states were ascertained on the sample. Emotion-modulated startle failed to differentiate between mood disordered individuals and healthy controls. However, results found a significant association between abnormal patterns of emotion responding and positive affect (PA), such that individuals with low PA showed exaggerated responding to unpleasant stimuli. The results suggest that PA may be an important dimension in mood disorders that underlies abnormal emotional responses.

L'alimentation des circuits à très faible tension, permettant une efficacité énergétique multipliée par 10, répond aux contraintes des applications mobiles, au prix d'une variabilité accrue limitant la prédiction des résultats et nécessitant des efforts et méthodologies de conception spécifiques. Cette thèse associe la conception à très faible tension aux exigences industrielles, et présente le développement de cellules digitales optimisées pour la très faible tension, par une méthodologie indépendante de la technologie. Ces cellules, validées par des mesures sur silicium en technologie CMOS 40nm, ont conduit à la fabrication d'un circuit numérique, dont le test met en évidence les adaptations permettant d'améliorer le rendement. Enfin, une cellule mémoire a été conçue et optimisée à très faible tension, ainsi que des solutions d'assistance en lecture et en écriture pour renforcer la tolérance à la variabilité. Un démonstrateur 128kb est fabriqué en 65nm pour valider ces développements.

Objective: Past research indicates that comorbid anxiety and depression in youth is associated with greater functional impairment than anxiety alone. To elucidate those factors which may increase vulnerability to depressive disorders, the current study examined several clinical correlates (i.e., feelings ratings, parental psychopathology symptoms, and family functioning) of comorbid depressive symptoms in young anxious children. Method: Sixty-eight children, aged 6 to 10 years (M = 9.06, SD = 1.10), and caregivers completed measures assessing child depressive symptoms. Furthermore, children completed self reports of anxiety symptoms, feelings ratings, and family functioning, while caregivers completed self reports of psychopathology symptoms and family functioning. Predictors of child depressive symptoms were examined separately for girls and boys. Results: In females, hierarchical regression analyses revealed that, after controlling for anxiety, higher sadness and lower positive feelings accounted for 30% of variance in child-reported depressive symptoms. Further analyses indicated that child-reported overall family dysfunction moderated the relationship between positive feelings and depressive symptoms, such that high family dysfunction increased the risk of depressive symptoms in females with low positive emotions. In males, hierarchical regression analyses revealed that, after controlling for anxiety, higher negative/hostile feelings and child-reported overall family dysfunction accounted for 19% of variance in child-reported depressive symptoms. Further analyses of family functioning in males revealed that child-reported family cohesion and conflict were negatively and positively correlated, respectively, with depressive symptoms. Family dysfunction did not moderate the relationship between feelings ratings and depressive symptoms. The only significant predictor of caregiver-reported child depressive symptoms, for males only, was caregiver self-reported overall psychopathology symptoms. Further analyses indicated that, for males, caregiver depression and hostility symptoms correlated positively with caregiver-reported child depressive symptoms. Conclusions: Different patterns of emotion and family functioning predicted self-reported depressive symptoms in males and females. Self and caregiver reports of child depressive symptoms were not related, with only caregivers’ psychopathology symptoms predicting their reports of child depressive symptoms. Results suggest the importance of assessing child-reported feelings and family dysfunction, and parental symptomatology, of clinically anxious children. To prevent future depressive disorders in these children, different targets of intervention for males and females may be warranted.

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.

Over the last 10 years, digital subthreshold logic circuits have been developed for applications in the ultra-low power design domain, where performance is not the priority. Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this thesis, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. The goal of this technique is to construct and inscribe a maximum yield cube in the 3-D feasible region composed of oxide thickness, gate length, and channel doping concentration. The center of this cube is chosen as the maximum yield design point with the highest immunity against variations. By using the technique, a transistor is optimized for subthreshold operation in terms of the desired total leakage current and intrinsic delay bounds. To develop the concept of the technique, sample devices are designed for 90nm and 65nm technologies. Monte Carlo simulations verify the accuracy of the technique for meeting power and delay constraints under technology-specific variances of the design parameters of the device.

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.

Over the last 10 years, digital subthreshold logic circuits have been developed for applications in the ultra-low power design domain, where performance is not the priority. Recently, devices optimized for subthreshold operation have been introduced as potential construction blocks. However, for these devices, a strong sensitivity to process variations is expected due to the exponential relationship of the subthreshold drive current and the threshold voltage. In this thesis, a yield optimization technique is proposed to suppress the variability of a device optimized for subthreshold operation. The goal of this technique is to construct and inscribe a maximum yield cube in the 3-D feasible region composed of oxide thickness, gate length, and channel doping concentration. The center of this cube is chosen as the maximum yield design point with the highest immunity against variations. By using the technique, a transistor is optimized for subthreshold operation in terms of the desired total leakage current and intrinsic delay bounds. To develop the concept of the technique, sample devices are designed for 90nm and 65nm technologies. Monte Carlo simulations verify the accuracy of the technique for meeting power and delay constraints under technology-specific variances of the design parameters of the device.

In this thesis, we carefully investigate the electrical characteristics of junctionless vertical MOSFET (JLVMOS) compared with the junctionless planar MOSFET (JLPMOS) and conversional junction vertical MOSFET (JVMOS). Also, we examine the advantages of the double-gate structure and the short-channel behavior of the junctionless transistors. According to the 2D simulation studies, the proposed JLVMOS can achieve better short-channel characteristics (JLVMOS: 62.04 mV/dec S.S., 23.96 mV/V DIBL; JLPMOS: 77.67 mV/dec S.S., 146.07 mV/V DIBL) as compared with the planar transistor, chiefly owing to the double-gate scheme. This proves that only the double-gate device has better gate controllability over the channel region to reduce the short-channel effect. More importantly is that the JLVMOS has a bulk Si starting material, in which the SOI-induced self-heating effects and the fabrication cost can be well suppressed and reduced, respectively. In comparison with the JVMOS, our proposed JLVMOS exhibits better S.S. and reduced DIBL. Furthermore, although the analog/RF properties of the JLVMOS are somewhat degraded, due to its simple fabrication process, our proposed JLVMOS can become one of the mainstream technology for future CMOS applications.

Modern electronics continues to push past boundaries of integration and functional density toward elusive, completely autonomous, self-powered microsystems. As systems continue to shrink, however, less energy is available on board, leading to short device lifetimes (run-time or battery life). Extended battery life is particularly advantageous in the systems with limited accessibility, such as biomedical implants and structure-embedded micro-sensors. The power management process usually requires compact and efficient power converters to be embedded in these microsystems. This dissertation introduces switched-capacitor (SC) power converter designs that make all these techniques realizable on silicon.Four different integrated SC power converters with multiple control schemes are designed here to provide low-power high-efficient power sources. First, a monolithic step-down power converter with subthreshold z-domain digital pulse-width modulation (DPWM) controller is proposed for ultra-low power microsystems. The subthreshold design significantly reduces the power dissipation in the controller. Second, an efficient monolithic master-slave complementary power converter with a feedback controller that purely operates in subthreshold operation region is discussed to tailor for the aforementioned ultra-low power applications. Third, we introduce an efficient monolithic step-down SC power stage with multiple-gain control and on-chip capacitor sizing for self-powered microsystems. The multiple-gain control helps the converter to constantly maintain high efficiency over a large input/output range. The size-adjustable pumping capacitors allow the output voltage to be regulated at different desired levels, with a constant 50% duty ratio. The monolithic implementations in these three integrated CMOS power converters effectively suppress noise and glitches caused by parasitic components due to bonding, packaging and PCB wiring. Fourth, an efficient step-up and step-down SC power converter with multiple-gain closed-loop controller is presented. The measurements and simulation results in these four power converters demonstrate the techniques proposed in this research. The approaches presented in this dissertation are evidently viable for realizing compact and high efficient SC power converters, contributing to next generation power-efficient microsystems designs.