Objective: Past research indicates that comorbid anxiety and depression in youth is associated with greater functional impairment than anxiety alone. To elucidate those factors which may increase vulnerability to depressive disorders, the current study examined several clinical correlates (i.e., feelings ratings, parental psychopathology symptoms, and family functioning) of comorbid depressive symptoms in young anxious children. Method: Sixty-eight children, aged 6 to 10 years (M = 9.06, SD = 1.10), and caregivers completed measures assessing child depressive symptoms. Furthermore, children completed self reports of anxiety symptoms, feelings ratings, and family functioning, while caregivers completed self reports of psychopathology symptoms and family functioning. Predictors of child depressive symptoms were examined separately for girls and boys. Results: In females, hierarchical regression analyses revealed that, after controlling for anxiety, higher sadness and lower positive feelings accounted for 30% of variance in child-reported depressive symptoms. Further analyses indicated that child-reported overall family dysfunction moderated the relationship between positive feelings and depressive symptoms, such that high family dysfunction increased the risk of depressive symptoms in females with low positive emotions. In males, hierarchical regression analyses revealed that, after controlling for anxiety, higher negative/hostile feelings and child-reported overall family dysfunction accounted for 19% of variance in child-reported depressive symptoms. Further analyses of family functioning in males revealed that child-reported family cohesion and conflict were negatively and positively correlated, respectively, with depressive symptoms. Family dysfunction did not moderate the relationship between feelings ratings and depressive symptoms. The only significant predictor of caregiver-reported child depressive symptoms, for males only, was caregiver self-reported overall psychopathology symptoms. Further analyses indicated that, for males, caregiver depression and hostility symptoms correlated positively with caregiver-reported child depressive symptoms. Conclusions: Different patterns of emotion and family functioning predicted self-reported depressive symptoms in males and females. Self and caregiver reports of child depressive symptoms were not related, with only caregivers’ psychopathology symptoms predicting their reports of child depressive symptoms. Results suggest the importance of assessing child-reported feelings and family dysfunction, and parental symptomatology, of clinically anxious children. To prevent future depressive disorders in these children, different targets of intervention for males and females may be warranted.

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

Boundary conditions for the cable equation - such as voltage-clamped or sealed cable ends, branchpoints, somatic shunts, and current clamps - result in multi-exponential series representations of the voltage or current. Each term in the series expansion is characterized by a decay rate (eigenvalue) and an initial amplitude (Fourier coefficient). The eigenvalues are determined numerically and the Fourier coefficients are subsequently given by the residues at the eigenvalues of the Laplace transform of the solution. In this paper, we introduce an alternative method for estimating the Fourier coefficients which works for all types of boundary conditions and is practical even when analytic expressions for the Fourier coefficients become intractable. It is shown that terms in the analytic expressions for the Fourier coefficients result from derivatives of the equation for the eigenvalues, and that simple numerical estimates for the amplitude coefficients are easily derived by replacing analytical derivatives by numerical eigenslope. The physical quantity represented by the slope is identified as effective neuron capacitance.

This dissertation discusses and compares the existing compensation methods for operational amplifiers. It explores a method to stabilize the op amps without sacrificing bandwidth to the same degree that commonly used methods do. A creative design methodology combining intuition, mathematical analysis, and mixed level simulation is explored for the new compensation scheme. The mixed level approach, associating system level simulation for most circuits along with device level simulation for some critical analog circuit paths, is presented to verify the behavior of new design concepts in an effective way. This approach also provides sufficient accuracy to predict the circuit performance realistically. The new feedforward compensation method overcomes the serious drawback of the widely used pole splitting method, which greatly narrows the bandwidth. It can improve the phase margin as well as optimize the bandwidth of the op amp. The proposed feedforward compensation method can be easily applied to the popular two gain stage op amp architectures with very little alteration. MOS devices are used in the weak inversion region or the subthreshold inversion region to minimize dc source power. A feasible configuration for high gain, low power op amp design utilizing subthreshold operation along with active operation is proposed. This op amp uses composite cascode connections for the differential input stage, a common source second stage, and a current mirror. A prototype of the op amp was fabricated in a 0.25 µm CMOS process. The proposed op amp produces an open loop gain above one million with low power consumption around 110 µW and shows a favorable slew rate and GBW product compared to other amplifiers driving large capacitive loads. In addition, the composite cascode amplifier requires a compensation capacitor of only 3.5 pF which allows a very small op amp cell. This design is intended for applications where simplicity of layout, small cell size, and low power are important. The open loop gain of this design is comparable to bipolar op amps and exceeds all known reported CMOS designs using the classic Widlar architecture. The fabricated op amp test results show that the BSIM3 model in CADENCE Spectre Spice Simulation matches closely to the experimental results in spite of the low current weak inversion operation of the composite cascode output device and thus provide confidence in the simulation for other similar designs. While facing the challenge of measuring the op amp open loop characteristics at decreased power supply voltages, a few viable techniques were developed to measure the op amp open loop parameters using typically available bench test equipment.

Op amps are among the most-used components in electronic design. Their performance is important and is often measured in terms of gain, bandwidth, power consumption, and chip area. Although BJT amplifiers can achieve high gains and bandwidths, they tend to consume a lot of power. CMOS amplifiers utilizing the strong inversion region alone use less power than BJT amplifiers, but generally have lower gains and bandwidths. When CMOS SPICE models were improved to accurately simulate all regions of inversion, researchers began to test the performance of amplifiers operating in the weak and moderate inversion regions. Previous work had dealt with exploring the parameters of composite cascode stages, including inversion coefficients. This thesis extends the work to include conventional cascode stages and presents an efficient method for exploring design parameters. A high-gain (137.7 dB), low power (4.347 µW) operational amplifier based on the conventional cascode stage is presented.

No description available.

Local field potentials (LFPs), extracellular potentials that reflect localized electrical activity, have long been used as a window to understand the behavioural dependence and mechanistic aspects of brain physiology. A principal premise that has driven the interpretation of LFPs is that they largely reflect the synaptic drive that impinges on neurons located in the vicinity of the recording microelectrode. An implicit, yet critical, assumption that led to the emergence of this premise is that dendrites, the structures onto which most synaptic inputs project, are purely passive compartments. However, there is a growing body of evidence demonstrating that dendrites express a plethora of active conductance, like voltage-gated ion channels, several of which are active in the subthreshold regime. These subthreshold-activated ion channels and their intra-neuronal localization profiles play widely acknowledged regulatory roles in the physiology, plasticity and pathophysiology of synapses and neurons. Despite this, the implications for the existence of these subthreshold conductances on constituent oscillatory patterns in LFPs and on the phase of neuronal spiking with reference to oscillating LFPs have surprisingly remained unexplored. The aim of this thesis is to examine if there exists a role of subthreshold conductances in regulating LFPs and the phase of spikes with reference to these LFPs. To address this, we chose to study LFPs and spikes from the CA1 region of the rat hippocampus, with hyperpolarization-activated cyclic-nucleotide-gated (HCN) channels forming the specific subthreshold conductance of focus. The reasons behind these choices were manifold. First, CA1 pyramidal neurons are arranged in a laminar open-field configuration, making the interpretation of the source-sink formation in this region relatively tractable. Second, the dendrites of these neurons are endowed with a multitude of subthreshold conductances whose expression profiles, physiology and plasticity have been characterized in great detail. Third, this brain region has been implicated in coding for episodic and spatial memories. The phase of the spikes of the CA1 pyramidal neurons, with reference to the LFP, is believed to serve as a code that can be used to decode the location of the animal. Given that the most dominant LFP pattern seen in the CA1 region during such active exploration (and possibly encoding of spatial memories) consists of oscillations in the 4–10 Hz theta frequency band, we decided to focus our study on theta-frequency LFPs. Finally, consistent with the choice of the specific band of LFP frequencies, we focused on HCN channels because of their predominantly dendritic expression and their ability to bestow resonance and impedance phase lead, both in the theta-frequency range, on CA1 pyramidal neurons. In exploring the role of HCN channels on LFPs, we used a multi-compartmental morphologically realistic CA1 pyramidal neuron model and introduced an HCN channel conductance gradient that was constrained with several experimental measurements. This neuron was driven by dendritic excitatory synapses and perisomatic inhibitory synapses, both theta-modulated with a phase difference of +60º between their arrivals timings. We increased the excitatory synaptic conductance with distance from the soma to account for the fact that irrespective of the location of the synapse in the dendrites, the unitary excitatory post-synaptic potential remains the same at the soma. Employing these model configurations, we generated 25 different synaptic distributions on the same neuronal morphology to account for the input variability and for each of these models, we recorded transmembrane currents from all the compartments, for 8–10 cycles of the theta-modulated inputs. To model LFPs using the forward modelling scheme of line source approximation, we designed a cylindrical neuropil of 40 µm height and 100 µm radius and inserted a virtual linear electrode with 7 contact points distributed on the probe at the canter of the neuropil such that we could compute the LFP at all the strata of the CA1 region. Accounting for the volume of the neuropil and the density of neurons in this region, we took 440 instances of the morphology, rotated them at uniformly distributed angles, and distributed the somata of these model neurons within the neuropil. Each of these 440 neurons received transmembrane currents from one of the 25 models picked uniformly. With a passive model, where we did not introduce HCN channels, we expectedly observed the formation of a source-sink structure that expressed as a progressive phase shift spanning different strata, owing to the perisomatic inhibitory currents coupled with the dendritic excitatory currents. On introducing a somatodendritic gradient of HCN conductance with identical input conditions, we observed a phase lead in the LFPs across all the layers, with the magnitude of the lead increasing with distance from the soma in a manner that was correlated with the increase in HCN conductance. Next, we computed spike phases, for each of the 25 neuron models, with reference to the stratum pyramidale (SP) LFP for model configurations with and without HCN channels. We found that the spikes showed a phase lag in the presence of a gradient of HCN channels when compared to the spike phases measured from the passive neuron models. Finally, we computed the coherence of spikes across all the 25 passive or 25 active (with HCN channels) neuron models and found that the presence of HCN channels greatly enhanced spike phase coherence across neurons. Together, these results demonstrate that the presence of HCN channels introduces a lead in the theta-frequency LFP phase, a lag in the associated spike phase, and a significant enhancement of spike phase coherence. Exploring the robustness of these findings to the model configuration, we first found these conclusions to be robust to increases in neuropil size (400-µm diameter neuropil with 1797 neurons, and 1-mm diameter neuropil with 11297 neurons). Next, we introduced heterogeneities in the population of neurons (in terms of morphology as well as passive and active properties) that formed the neuropil, and found our conclusions to be invariant to such degeneracy in the underlying neuronal population. It has been observed that under certain pathological conditions like epilepsy, an entire population of CA1 neurons can undergo intrinsic plasticity, such as global (i.e., across the entire neuronal topograph) downregulation of HCN channels. To assess the impact of such up/downregulation on LFPs, we respectively increased/decreased HCN channel conductance globally in our model neurons, and found the magnitude of the lead in the LFP phase to progressively increase with HCN-channel conductance. Similarly, the magnitude of the spike-phase lag and the spike phase coherence also progressively increased as functions of HCN-channel conductance. Although such population-level global intrinsic plasticity is observed under pathological conditions, a more physiological scenario would be when a single neuron, in the process of encoding new inputs (such as encoding spatial or episodic memories), undergoes intrinsic plasticity. To assess this, we increased or decreased HCN-channel conductance specifically in a single neuron placed closest to the electrode, while leaving the HCN expression in other neurons of the neuropil at the baseline level. Expectedly, we did not find significant changes in LFP amplitude or phase, but we did find a significant lag in the spike phase preference of the neuron that underwent an upregulation of HCN conductance. Another physiological scenario is when the rat experiences a reward or exhibits anxiety-like behaviour, which can lead to changes in hormonal or neuromodulator concentrations. These changes, functioning through the activation of G-protein coupled receptors and the consequent elevation of cytosolic cyclic adenosine monophosphate (cAMP) concentrations, could shift the half-maximal activation voltage ( V1/2 ) of HCN channels to a more depolarized potential. Would such a shift in V1/2 impact LFPs and spike phases in a manner similar to that observed with increasing the conductance of HCN channels? Assessing this within our modeling framework, we found that shifting the V1/2 by +5 mV resulted in an increased lead in the LFP phase, an increased lag in the spike phase and an enhanced spike phase coherence compared to the case with a hyperpolarized V1/2 . What are the biophysical mechanisms that underlie these robust changes observed in LFPs and spike phases observed as a consequence of these several ways of increasing the current through HCN channels? We reasoned that our observations could be explained by one of the two distinct changes conferred on CA1 pyramidal neuron physiology by the presence of HCN channels. First, in the presence of HCN channels, the voltage response of CA1 pyramidal neurons shows a phase lead with reference to a sinusoidal current input (inductive phase lead) in the theta frequency range. Second, HCN channels regulate the excitability of these cells by decreasing the input resistance and impedance amplitude. To delineate the differential role of the inductive changes vs. changes in excitability, we replaced HCN channels by a faster variant (HCNFast) such that neuronal excitability remained the same while abolishing the inductive phase lead in the theta band. On doing so, we found that the lead in the LFP phase and the lag in the spike phase brought about by HCN channels was partially reversed when HCN conductance values were low. However the reversal was not substantial when HCN conductance values were high, suggesting that the inductive phase component dominates at lower HCN channel conductances, whereas the excitability component plays a critical role at higher HCN conductances. Akin to intrinsic plasticity mentioned above, under certain pathological conditions, an entire population of neurons can undergo scaling of their excitatory or inhibitory synapses. In assessing the implications for such synaptic plasticity, we first found that our conclusions on the roles of HCN channels in introducing a lead in the LFP phase, a lag in the spike phase and an enhancement of spike phase coherence were invariant to the specific values of synaptic conductances, or the phase difference between excitatory and inhibitory theta-modulated inputs. While these observations further established the robustness of the changes brought about by HCN channels to LFPs and associated spikes, we next asked whether synaptic plasticity, mediated by changes in subthreshold synaptic conductances, could itself bring about changes in the LFP and spike phase. Expectedly, we found that scaling up of excitatory synapses introduced a mild lag in the LFP phase and a lead in the spike phase, whereas scaling up of inhibitory synapses introduced a lead in the LFP phase and a lag in the spike phase. Finally, we observed a critical role of the arrival phase of inhibition with reference to excitation in altering both, the stratum pyramidale LFP and associated spike phases, with the magnitude of change in both the LFP and the spike phase roughly following the magnitude of the shift in the excitatory-inhibitory phase difference. However, in contrast to changes observed with HCN-channel plasticity, there was no significant change in spike phase coherence with any of the three forms of synaptic changes explored. Together, our results identify definite roles for HCN channels and synaptic receptors in phase-coding schemas and in the formation and dynamic reconfiguration of neuronal cell assemblies and present a clear case for the incorporation of subthreshold-activated ion channels, their gradients, and their plasticity into the computation of LFPs. Given the rich expression of several subthreshold ion channels — including HCN, A-type potassium and T-type calcium — in neuronal dendrites, future work could focus on the impact of subthreshold channels on LFPs recorded in different brain regions under different behavioral states. This thesis is organized into seven chapters. Chapter 1 provides the motivations for the study, introduces the aim of the study and poses the specific questions asked in our endeavor to understand the role of subthreshold conductances in regulating LFPs and spike phases. Chapter 2 discusses the physiological foundations and relevant literature that places the questions posed in the first chapter in the context of the aim of the thesis, with an emphasis on the literature on HCN channels. In chapter 3, we introduce the computational and theoretical foundations required to model neurons and to compute LFPs. In chapter 4, we look at the consequences of the presence of a non-uniform density of somatodendritic HCN channels on LFPs and spike phase and test the robustness of the effects observed. In chapter 5, we present our assessment of the impact of intrinsic plasticity/modulation of HCN channels on LFPs and spike phases, also exploring the biophysical mechanisms underlying such an impact. In chapter 6, we test if the observed effects still hold under synaptic plasticity, and assess the regulation of LFPs and spike phases by synaptic changes. In chapter 7, we summarize and conclude the results presented in the preceding chapters and provide some potential directions for future studies.

Este trabalho apresenta o estudo de transistores de tunelamento controlados por efeito de campo, denominados TFETs. Foram realizadas análises com base em explicações teóricas, simulações numéricas e medidas experimentais para demonstrar a viabilidade do uso desta tecnologia em blocos de circuitos fundamentais, atuando como alternativa para permitir o contínuo escalamento de dispositivos. A motivação para o uso de transistores com corrente principal resultante do tunelamento de banda para banda consiste na proposta de superar o limite físico de inclinação de sublimiar da tecnologia CMOS convencional de 60 mV/década sob temperatura ambiente. Afinal, esta limitação impede a redução na tensão de alimentação de circuitos e, consequentemente, apresenta crescentes problemas quanto à dissipação de potência. Com este objetivo, foram realizadas simulações numéricas de diversas geometrias alternativas visando atenuar as características indesejáveis dos TFETs, como a corrente ambipolar e a relativamente baixa relação ION/IOFF. Inicialmente foram definidos os modelos necessários para representar adequadamente os fenômenos relevantes sob variação de temperatura e é definida uma estrutura capaz de minimizar os efeitos da ambipolaridade. Posteriormente, medidas experimentais foram utilizadas para calibrar as simulações e estudar o efeito da temperatura e do dimensionamento no funcionamento de dispositivos desta tecnologia. Comparando resultados práticos e simulados, nota-se como uma redução no comprimento de porta, com a consequente inserção de uma subposição (underlap) em relação à junção canal/dreno, e uma diminuição na temperatura permitem a obtenção de valores promissores de inclinação de sublimiar e de relação ION/IOFF. Com base nestes resultados individuais, foram projetados circuitos básicos de aplicações analógicas, notadamente espelho de corrente e par diferencial, para a avaliação da viabilidade de duas diferentes estruturas de transistores de tunelamento. Foram realizadas medidas experimentais e simulações numéricas de ambos os circuitos com variações nas condições de polarização, na situação de descasamento entre os dispositivos e na temperatura de operação. O impacto em parâmetros fundamentais dos circuitos estudados, como a tensão de conformidade, a razão de espelhamento de corrente e o ganho de tensão diferencial, foi comparado para estruturas de tunelamento pontual (Point TFET), de tunelamento em linha (Line TFET) e de FinFETs. Em relação aos circuitos de espelhos de corrente, observou-se alta tensão de conformidade e baixa dependência com a temperatura para os circuitos com transistores de tunelamento. O Point TFET ainda apresentava a vantagem adicional da baixa susceptibilidade ao descasamento do comprimento de canal, porém com a desvantagem da baixa magnitude da corrente de referência quando comparado ao espelho com Line TFETs ou FinFETs. Já no caso de pares diferenciais, a maior tensão de conformidade foi obtida com FinFETs, enquanto os transistores de tunelamento apresentaram em comum a não degradação do ganho com a temperatura. Novamente o circuito com Point TFETs apresentou melhor resultado quando houve descasamento, enquanto que as outras duas tecnologias foram superiores quando ao ganho de tensão diferencial. Dessa forma, foram propostas equações generalizadas para os parâmetros fundamentais de ambos os circuitos para as 3 tecnologias. De modo geral, foi possível validar, portanto, a viabilidade de transistores de tunelamento para a obtenção de dispositivos com bons parâmetros individuais e com bons impactos em circuitos analógicos fundamentais, reforçando a importância desta promissora tecnologia. / This works presents the study of tunneling field effect transistors, namely TFETs. Analyses have been performed based on theoretical explanations, numerical simulations and experimental data in order to show this technology suitability as part of basic circuit blocks, being an important alternative for the continuous devices scaling. The basic idea of making use of band-to-band tunneling as the main current component comes from the possibility of reaching sub-60 mV/decade subthreshold slopes at room temperature, differently from conventional CMOS devices. After all, this physical limitation causes relevant power dissipation issues, since it requires relatively high power supply voltages. Bearing this objective, numerical simulations of several alternative geometries have been performed in order to tackle TFETs disadvantages, such as the undesirable ambipolar currents and the low ION/IOFF ratio. At first, it was necessary to choose the most appropriate models to take into consideration the relevant phenomena under temperature variation and to define the physical structure in order to minimize ambipolar effects. After these analyses, experimental data have been used to calibrate simulation parameters and to study how temperature and physical dimensions affect the performance of devices based on this technology. Comparing experimental and simulated results, it was possible to notice that when the structure is designed with gate underlap related to channel/drain junction and the temperature decreases, it was possible to obtain promising values for subthreshold slope and ION/IOFF ratio. Based on the analyses of these individual results, basic analog circuits have been designed, namely current mirror and differential pair, so that two different tunneling devices structures have been highlighted. Experimental measurements and numeric simulations have been performed for both circuits, under different conditions in terms of bias voltages, channel length mismatch and operation temperature. The impact on fundamental circuit parameters, such as compliance voltage, current mirroring ratio and differential voltage gain, has been compared for circuits designed with Point TFETs, Line TFETs and FinFETs. Regarding current mirror circuits, the obtained results revealed higher values of compliance voltage and lower susceptibility to the temperature for circuits designed with tunneling transistors. In addition, Point TFETs provided the lowest susceptibility to channel length mismatch, but also the worst values of reference currents, when compared to circuits with Line TFETs and FinFETs. Following the same procedure for differential pair, higher compliance voltage was obtained for FinFETs, while both tunneling transistors structures presented better behavior for differential voltage gain susceptibility to temperature variation. Once more, pairs with Point TFETs showed the best performance in terms of channel length mismatch, but the worst magnitude of differential voltage gain. This way, general equations have been proposed to model relevant parameters for the circuits designed with each technology. From an overall point of view, it was possible to support the suitability of optimizing tunneling transistors in order to obtain devices with favorable individual parameters and positive impacts on essential analog circuits, reassuring the relevance of this promising technology.

Este trabalho apresenta o estudo de transistores de tunelamento controlados por efeito de campo, denominados TFETs. Foram realizadas análises com base em explicações teóricas, simulações numéricas e medidas experimentais para demonstrar a viabilidade do uso desta tecnologia em blocos de circuitos fundamentais, atuando como alternativa para permitir o contínuo escalamento de dispositivos. A motivação para o uso de transistores com corrente principal resultante do tunelamento de banda para banda consiste na proposta de superar o limite físico de inclinação de sublimiar da tecnologia CMOS convencional de 60 mV/década sob temperatura ambiente. Afinal, esta limitação impede a redução na tensão de alimentação de circuitos e, consequentemente, apresenta crescentes problemas quanto à dissipação de potência. Com este objetivo, foram realizadas simulações numéricas de diversas geometrias alternativas visando atenuar as características indesejáveis dos TFETs, como a corrente ambipolar e a relativamente baixa relação ION/IOFF. Inicialmente foram definidos os modelos necessários para representar adequadamente os fenômenos relevantes sob variação de temperatura e é definida uma estrutura capaz de minimizar os efeitos da ambipolaridade. Posteriormente, medidas experimentais foram utilizadas para calibrar as simulações e estudar o efeito da temperatura e do dimensionamento no funcionamento de dispositivos desta tecnologia. Comparando resultados práticos e simulados, nota-se como uma redução no comprimento de porta, com a consequente inserção de uma subposição (underlap) em relação à junção canal/dreno, e uma diminuição na temperatura permitem a obtenção de valores promissores de inclinação de sublimiar e de relação ION/IOFF. Com base nestes resultados individuais, foram projetados circuitos básicos de aplicações analógicas, notadamente espelho de corrente e par diferencial, para a avaliação da viabilidade de duas diferentes estruturas de transistores de tunelamento. Foram realizadas medidas experimentais e simulações numéricas de ambos os circuitos com variações nas condições de polarização, na situação de descasamento entre os dispositivos e na temperatura de operação. O impacto em parâmetros fundamentais dos circuitos estudados, como a tensão de conformidade, a razão de espelhamento de corrente e o ganho de tensão diferencial, foi comparado para estruturas de tunelamento pontual (Point TFET), de tunelamento em linha (Line TFET) e de FinFETs. Em relação aos circuitos de espelhos de corrente, observou-se alta tensão de conformidade e baixa dependência com a temperatura para os circuitos com transistores de tunelamento. O Point TFET ainda apresentava a vantagem adicional da baixa susceptibilidade ao descasamento do comprimento de canal, porém com a desvantagem da baixa magnitude da corrente de referência quando comparado ao espelho com Line TFETs ou FinFETs. Já no caso de pares diferenciais, a maior tensão de conformidade foi obtida com FinFETs, enquanto os transistores de tunelamento apresentaram em comum a não degradação do ganho com a temperatura. Novamente o circuito com Point TFETs apresentou melhor resultado quando houve descasamento, enquanto que as outras duas tecnologias foram superiores quando ao ganho de tensão diferencial. Dessa forma, foram propostas equações generalizadas para os parâmetros fundamentais de ambos os circuitos para as 3 tecnologias. De modo geral, foi possível validar, portanto, a viabilidade de transistores de tunelamento para a obtenção de dispositivos com bons parâmetros individuais e com bons impactos em circuitos analógicos fundamentais, reforçando a importância desta promissora tecnologia. / This works presents the study of tunneling field effect transistors, namely TFETs. Analyses have been performed based on theoretical explanations, numerical simulations and experimental data in order to show this technology suitability as part of basic circuit blocks, being an important alternative for the continuous devices scaling. The basic idea of making use of band-to-band tunneling as the main current component comes from the possibility of reaching sub-60 mV/decade subthreshold slopes at room temperature, differently from conventional CMOS devices. After all, this physical limitation causes relevant power dissipation issues, since it requires relatively high power supply voltages. Bearing this objective, numerical simulations of several alternative geometries have been performed in order to tackle TFETs disadvantages, such as the undesirable ambipolar currents and the low ION/IOFF ratio. At first, it was necessary to choose the most appropriate models to take into consideration the relevant phenomena under temperature variation and to define the physical structure in order to minimize ambipolar effects. After these analyses, experimental data have been used to calibrate simulation parameters and to study how temperature and physical dimensions affect the performance of devices based on this technology. Comparing experimental and simulated results, it was possible to notice that when the structure is designed with gate underlap related to channel/drain junction and the temperature decreases, it was possible to obtain promising values for subthreshold slope and ION/IOFF ratio. Based on the analyses of these individual results, basic analog circuits have been designed, namely current mirror and differential pair, so that two different tunneling devices structures have been highlighted. Experimental measurements and numeric simulations have been performed for both circuits, under different conditions in terms of bias voltages, channel length mismatch and operation temperature. The impact on fundamental circuit parameters, such as compliance voltage, current mirroring ratio and differential voltage gain, has been compared for circuits designed with Point TFETs, Line TFETs and FinFETs. Regarding current mirror circuits, the obtained results revealed higher values of compliance voltage and lower susceptibility to the temperature for circuits designed with tunneling transistors. In addition, Point TFETs provided the lowest susceptibility to channel length mismatch, but also the worst values of reference currents, when compared to circuits with Line TFETs and FinFETs. Following the same procedure for differential pair, higher compliance voltage was obtained for FinFETs, while both tunneling transistors structures presented better behavior for differential voltage gain susceptibility to temperature variation. Once more, pairs with Point TFETs showed the best performance in terms of channel length mismatch, but the worst magnitude of differential voltage gain. This way, general equations have been proposed to model relevant parameters for the circuits designed with each technology. From an overall point of view, it was possible to support the suitability of optimizing tunneling transistors in order to obtain devices with favorable individual parameters and positive impacts on essential analog circuits, reassuring the relevance of this promising technology.