Studies indicate that there will be an increase in precipitation and flooding in cities due to coming climate changes. The current stormwater management systems in Stockholm are not equipped to handle such a change. This necessitates a momentum towards sustainable stormwater solutions. This paper intends to examine from a Niche Providers' perspective what a sustainable stormwater solution in Stockholm could entail, to which extent it is being implemented and what the perceived barriers are towards a regime shift, using Strategic Niche Management theory as a framework. The Niche Providers interviewed were in agreement that LOD (local management of stormwater) is the desired solution for sustainable stormwater management in Stockholm. This was also supported by the literature. When asked how far the implementation of LOD has come in Stockholm, the Niche Providers were unable to provide concrete answers. Their answers indicated however, that attempts are being made to as far as possible work with LOD. The research shows that despite this, there has been no significant change in the overall implementation of LOD in recent years showing that there is in fact inertia towards regime shift. Through the interviews conducted the Niche Providers were given an opportunity to articulate what they saw as barriers towards using LOD solutions both in their everyday life and in the industry in general. An analysis of the data provided through these interviews gives a good indication of what these Niche Providers perceive as being obstacles that explain the inertia towards a regime shift. The biggest perceived barriers were Governmental and regulatory factors, Technological factors and Demand factors. These results correspond well with the strategic niche management theory that shows that in order for a regime shift to occur, you first and foremost need to have a viable technological solution, but you also require the government to take active measures in order to ensure forward momentum as a way to counteract the significant barrier provided on the demand side. However, the research indicates that the inertia towards LOD might be coming to an end as there have been some significant steps taken in one of the biggest barriers, the governmental and regulatory framework factor. / Studier visar att förväntade klimatförändringar kommer att innebära en ökning av nederbörd och översvämningar i städer. De nuvarande systemen för dagvattenhanteringen i Stockholm är inte utrustade för att hantera en sådan förändring, varför det krävs en övergång till hållbara dagvattenlösningar. Detta kandidatexamensarbete har för avsikt att undersöka vad en hållbar dagvattenlösning i Stockholm skulle kunna innebära och i vilken utsträckning en sådan lösning redan implementeras. Arbetet har även som huvudsyfte att utreda, inom ramen för den strategiska nischhanteringsteorin, vad som upplevs vara hindren mot att helt gå över till en hållbar lösning, ett så kallat regimskifte. Detta har gjorts genom att intervjua nischleverantörer. Dessa var överens om att LOD (lokalt omhändertagande av dagvatten) är den önskade lösningen för hållbar dagvattenhantering i Stockholm, en åsikt som även har stöd i litteraturen. Vid förfrågan om hur långt implementeringen av LOD har kommit i Stockholm kunde dessa nischleverantörer inte ge konkreta svar. Deras svar indikerade emellertid att försök görs att så långt som möjligt arbeta med LOD. Forskning från de senaste åren visar dock att det trots dessa försök inte har skett någon markant förändring i LOD-användningens omfattning. Av detta kan slutsatsen fastslås att det finns en tröghet mot regimskifte. Genom de intervjuer som genomfördes fick nischleverantörerna möjlighet att formulera vad de, i sin vardag och i branschen i allmänhet, ansåg utgöra hinder mot genomförbarheten av LOD. En analys av dessa uppgifter ger en bra indikation på vad dessa nischleverantörer uppfattar som hindrande faktorer som orsakar trögheten mot ett regimskifte. De största upplevda hindren var statliga och reglerande faktorer, tekniska faktorer och faktorer gällande efterfrågan. Dessa resultat överensstämmer med den strategiska nischhanteringsteorin som hävdar att för ett regimskifte krävs först och främst en lönsam teknisk lösning. För att den tekniska lösningen ska kunna slå rot förutsätts dock att regeringen vidtar aktiva åtgärder för att motverka de betydande hinder som finns på efterfrågesidan. Den forskning som lagts fram i denna studie tyder emellertid på att det sker en positiv förändring avseende trögheten mot LOD eftersom det har skett betydande framsteg inom den statliga sektorn, vilket har upplevts utgöra ett av de största hindren.

Detection of special nuclear material (SNM) being smuggled into the US through ports of entry has been identified as a crucial capability for ensuring the safety and security of the US from radiological threats. Programs such as the NNSA's Second Line of Defense aim to deploy detection systems, both domestically and abroad, in an attempt to interdict the SNM before it reaches its destination. Active interrogation (AI) is a technique that relies on the detection of emitted particles which are produced when SNM is bombarded with a source of high energy photons or neutrons. This work presents a general framework that allows for fast radiation transport modeling of AI scenarios by generating families of response functions which depict neutron, gamma, or electron radiation exiting various regions within the problem, per unit source of radiation entering the region. The solution for a given scenario, typically the detector count rate, is computed by injecting a source term into the first region and applying the appropriate response functions, in sequence, for each subsequent region. For the AI systems modeled in this work, the source is an electron beam in a linear accelerator. Subsequent response functions create and transport bremsstrahlung photons into the SNM, and transport neutrons born in the problem to a detector. The computed solution is comparable to that of a full Monte Carlo simulation, but is assembled in orders of magnitude less time from pre-computed response function libraries. The ability to rapidly compute detector spectra for complicated AI scenarios opens up research and analysis possibilities not previously possible, including conducting parametric studies of scenarios spanning a large portion of the threat space and generating detector spectra used for conditioning and testing of alarm algorithms. / text

This mixed methods study aims at evaluating the transformative potential of Nationally Appropriate Mitigation Actions (NAMAs). Earlier studies on the subject have outlined a lack of clarity both on the concept of NAMAs and on how developing countries will use it in their climate actions and thus its ability to contribute to transformational change. The mixed method approach used was: quantitative content analysis of Intended Nationally Determined Contribution (INDC) from developing countries referring to NAMAs combined with qualitative thematic analysis of NAMA proposals from eight selected countries. An explanatory sequential design was used which means that the first quantitative phase aimed at giving an initial understanding of NAMAs transformative potential. The purpose with the second phase, the qualitative analysis was then to deepen that understanding, by applying transformation theories. The two phases of analysis was integrated in the discussion section to get a more complete picture of the transformative potential. The result shows that the intent with NAMAs in the INDC consists of great uncertainties. A variety of NAMA designs was found in both phases of the study. In all of the eight more closely studied countries elements of transformation could be identified, which indicates that NAMAs could be designed to have transformative potential.

Drosophila male is an example of achiasmatic meiosis which lacks crossingover and chiasmata during meiosis. Previous studies showed that homologous pairing of both euchromatin and centromeres is lost during middle prophase I, however, homologs are still connected as they form bivalents. The X-Y pair utilizes a specific repeated sequence within the heterochromatic ribosomal DNA blocks as a pairing site. No pairing sites have yet been identified for the autosomes. To search for such sites, we utilized probes specifically targeting heterochromatin regions to assay pairing sequences and behavior in meiosis by fluorescence in situ hybridization (FISH). We found that the fourth homologs pair at the heterochromatic region 61 and associate with the X chromosome throughout prophase I. The pairing of the fourth homologs is disrupted in the homolog conjunction complex mutants. Conversely, six tested heterochromatic regions of the major autosomes (second and third chromosomes) have proved to be largely unpaired after early prophase I. This suggests that pairing mechanism of the major autosomes may differ from the sex and fourth chromosomes; stable connections between major autosomal homologs might occur at different sites along chromosomes in different cells by analogy to chiasmata. Moreover, FISH analysis also revealed two distinct patterns of sister chromatid cohesion in heterochromatin: regions with stable cohesion and regions lacking cohesion, suggesting that sister chromatid cohesion is incomplete within heterochromatin but with preferential sites in male meiosis.Modifier of Mdg4 in Meiosis (MNM) and Stromalin in Meiosis (SNM) are components of homolog conjunction complex and essential for homolog pairing and segregation in male meiosis. Using yeast two-hybrid assay and co-immunoprecipitation, we showed that the MNM and SNM interact with each other. Specifically, the BTB domain of MNM is responsible for the interaction with SNM, whereas FLYWCH domain of MNM is crucial for this interaction but does not directly interact with SNM. Additionally, point mutation analysis revealed that L9K replacement of the BTB domain weakened the MNM-SNM interaction and caused high frequencies of chromosome nondisjunction. In conclusion, these results provide a biochemical basis for the mechanism of homolog pairing and support the role of homolog conjunction complex in male meiosis.

Yield analysis is a critical step in memory designs considering a variety of performance constraints. Traditional circuit level Monte-Carlo simulations for yield estimation of Static Random Access Memory (SRAM) cell is quite time consuming due to their characteristic of low failure rate, while statistical method of yield sensitivity analysis is meaningful for its high efficiency. This thesis proposes a novel statistical model to conduct yield sensitivity prediction on SRAM cells at the simulation level, which excels regular circuit simulations in a significant runtime speedup. Based on the theory of Kriging method that is widely used in geostatistics, we develop a series of statistical model building and updating strategies to obtain satisfactory accuracy and efficiency in SRAM yield sensitivity analysis. Generally, this model applies to the yield and sensitivity evaluation with varying design parameters, under the constraints of most SRAM performance metric. Moreover, it is potentially suitable for any designated distribution of the process variation regardless of the sampling method.

<p>This thesis presents a novel six-transistor SRAM intended for advanced</p><p>microprocessor cache application. The objectives are to reduce power</p><p>consumption through scaling the supply voltage and to design a SRAM that is fully process-variation-tolerant, utilizing separate read and write access ports as well as exploiting asymmetry. Traditional six-transistor SRAM is designed and its strengths and weaknesses are discussed in detail. Afterwards, a new SRAM technology developed in the division of Electronic Devices, Linköping University is proposed and its capabilities and drawbacks are illustrated deeply. Subsequently, the impact of mismatch and process variation on both standard 6T and proposed asymmetric 6T SRAM cells is investigated. Eventually, the cells are compared regarding the voltage scalability, stability, and tolerability to variations in process parameters. It is shown that the new cell functions in 430mV while maintaining acceptable SNM margin in all process corners. It is also demonstrated that the proposed SRAM is fully process-variation-tolerant.</p><p>Additionally, a dual-V t asymmetric 6T cell is introduced having wide SNM margin comparable with that of conventional 6T cell such that it is capable of functioning in 580mV.</p>

This thesis presents a novel six-transistor SRAM intended for advanced microprocessor cache application. The objectives are to reduce power consumption through scaling the supply voltage and to design a SRAM that is fully process-variation-tolerant, utilizing separate read and write access ports as well as exploiting asymmetry. Traditional six-transistor SRAM is designed and its strengths and weaknesses are discussed in detail. Afterwards, a new SRAM technology developed in the division of Electronic Devices, Linköping University is proposed and its capabilities and drawbacks are illustrated deeply. Subsequently, the impact of mismatch and process variation on both standard 6T and proposed asymmetric 6T SRAM cells is investigated. Eventually, the cells are compared regarding the voltage scalability, stability, and tolerability to variations in process parameters. It is shown that the new cell functions in 430mV while maintaining acceptable SNM margin in all process corners. It is also demonstrated that the proposed SRAM is fully process-variation-tolerant. Additionally, a dual-V t asymmetric 6T cell is introduced having wide SNM margin comparable with that of conventional 6T cell such that it is capable of functioning in 580mV.

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%). / The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).