I propose compact models of single-gate (SG) and double-gate (DG) JFETs predicting the current-voltage characteristics for both long and short channel devices. In order to make the current equation continuous through all operating conditions from subthreshold to well-above threshold, without non-physical fitting parameters, mobile carriers in depletion region are considered. For describing the short channel behavior, relevant parameters extracted from the two-dimensional analytical solution of Poisson's equation are used for modifying long channel equations. Comparisons of models with the numerical simulation showing close agreement are presented. Based on models, merits of DG JFET over SG JFET and SG MOSFET are discussed by examining the schematic circuit diagram describing the relation between gate and channel potentials for each device. / text

In this thesis, we carefully investigate the electrical characteristics of junctionless vertical MOSFET (JLVMOS) compared with the junctionless planar MOSFET (JLPMOS) and conversional junction vertical MOSFET (JVMOS). Also, we examine the advantages of the double-gate structure and the short-channel behavior of the junctionless transistors. According to the 2D simulation studies, the proposed JLVMOS can achieve better short-channel characteristics (JLVMOS: 62.04 mV/dec S.S., 23.96 mV/V DIBL; JLPMOS: 77.67 mV/dec S.S., 146.07 mV/V DIBL) as compared with the planar transistor, chiefly owing to the double-gate scheme. This proves that only the double-gate device has better gate controllability over the channel region to reduce the short-channel effect. More importantly is that the JLVMOS has a bulk Si starting material, in which the SOI-induced self-heating effects and the fabrication cost can be well suppressed and reduced, respectively. In comparison with the JVMOS, our proposed JLVMOS exhibits better S.S. and reduced DIBL. Furthermore, although the analog/RF properties of the JLVMOS are somewhat degraded, due to its simple fabrication process, our proposed JLVMOS can become one of the mainstream technology for future CMOS applications.