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Thesis (M.S.)--University of Texas at Dallas, 2006 / Includes vita. Includes bibliographical references (leaves 97-98)

This thesis describes the design, implementation and testing of a UHF frequency synthesizer. The synthesizer is designed to provide a sine wave output programmable from 400 MHz to 500 MHz in 0.1 MHz increments. The synthesis technique utilized is Digital Coherent Indirect Synthesis. This technique uses phase locking to provide a range of stable output frequencies all derived from a single crystal reference. Component design and system level analysis are presented in detail.

In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency divider have been realized using dynamic precharge-evaluation logic. Moreover, a non-conventional method to implement non-power-of-2 division ratios has been used for the higher frequency divider stages (input stages).

Το αντικείμενο της παρούσας διπλωματικής εργασίας είναι ο σχεδιασμός και η υλοποίηση ενός ταλαντωτή εμβολής, ο οποίος θα μπορεί να χρησιμοποιηθεί και ως διαιρέτης συχνοτήτων. Ο ταλαντωτής και ο διαιρέτης συχνοτήτων, αποτελούν εξέχουσας σημασίας δομικά στοιχεία των RF πομποδεκτών και τοποθετούνται κατά κύριο λόγο μέσα στο βρόχο κλειδώματος φάσης-PLL, ο οποίος επιλέγεται ως συνθέτης συχνοτήτων στα περισσότερα ασύρματα τηλεπικοινωνιακά συστήματα. Αφού μελετήσαμε τη δομή και τις κυριότερες τοπολογίες που χρησιμοποιούνται στη σχεδίαση των ταλαντωτών, προχωρήσαμε στην ανάλυση της εφαρμογή της μεθόδου της εμβολής (injection locking), με σκοπό τη βελτίωση των χαρακτηριστικών της εξόδου τους και ιδιαίτερα τη μείωση του θορύβου φάσης. Επίσης, περιγράφονται τα βασικά χαρακτηριστικά των αναλογικών και των ψηφιακών διαιρετών, ενώ δίνεται ιδιαίτερη έμφαση στην ανάλυση της λειτουργίας των αναλογικών διαιρετών συχνότητας που βασίζονται σε ταλαντωτές εμβολής και είναι ευρύτερα γνωστοί ως injection-locked διαιρέτες συχνότητας (ILFDs). Η επιλογή για περαιτέρω μελέτη και υλοποίηση ενός Colpitts και ενός διαφορικού ταλαντωτή, βασίστηκε στα πλεονεκτήματα που παρουσιάζουν οι συγκεκριμένες τοπολογίες, με αποτέλεσμα την ευρεία χρήση τους σε RF εφαρμογές υψηλών συχνοτήτων. Επίσης οι ταλαντωτές εμβολής που προκύπτουν από τους ταλαντωτές αυτούς, επιδεικνύουν χαμηλή κατανάλωση ισχύος και πολύ καλή συμπεριφοράς ως προς τον θόρυβο φάσης. Ως συχνότητα λειτουργίας των προτεινόμενων κυκλωμάτων, επιλέχθηκε η πολύ σημαντική για τα ασύρματα συστήματα τηλεπικοινωνιών, συχνότητα των 5GHz. Προτείνεται και υλοποιείται λοιπόν ένας Colpitts ταλαντωτής και ο αντίστοιχος ταλαντωτής εμβολής, όπου όπως αποδεικνύεται τόσο από τις εξομοιώσεις όσο και από τα πειραματικά αποτελέσματα, μπορεί να λειτουργεί ως διαιρέτης συχνότητας δια-2 (Divide-by-2 ILFD). Από τα αποτελέσματα που προέκυψαν από τη μέτρηση του υλοποιημένου ταλαντωτή εμβολής, γίνεται ακόμη αντιληπτό ότι ο θόρυβος φάσης είναι εμφανώς βελτιωμένος, όπως αναμενόταν λόγω της εφαρμογής του σήματος εμβολής. Τέλος, σχεδιάστηκε και εξομοιώθηκε ένας διαφορικός ταλαντωτής (differential oscillator), από τον οποίο με κατάλληλη τροποποίηση της τοπολογίας του, προέκυψε ένας injection-locked divide-by-2 διαιρέτης συχνότητας. Το συγκεκριμένο κύκλωμα χρησιμοποιείται ευρέως για τη λειτουργία της διαίρεσης δια-2, εξαιτίας του ότι η τοπολογία του παρέχει ένα φυσικό divide-by-2 injection σημείο. / The subject of the present diplomatic project is the design and implementation of an injection locked oscillator, which might also be used as a frequency divider. The oscillator and the frequency divider, constitute distinguished important structural elements of RF transceivers and are mostly placed into the phase-locked-loop (PLL), which is selected as frequency synthesizer in most wireless telecommunications systems. After we studied the structure and the main topologies used in the design of oscillators, we advanced in the analysis and the application of injection locking method, aiming at the improvement of characteristics of their output and particularly the reduction of phase noise. Also, the basic characteristics of analog and digital dividers are described, while particular emphasis is given in the analysis of operation of analog frequency dividers that is based on injection-locked oscillators, more widely known as injection-locked frequency dividers (ILFDs). The choice for further study and implementation of a Colpitts and differential oscillator, was based on the advantages of the particular topologies, which result in their wide use in high-frequencies RF applications. Also the injection-locked oscillators that result from these oscillators, demonstrate low power consumption and very good behavior as far the phase noise. As operation frequency for the proposed circuits, was selected the very important for the wireless telecommunications systems, frequency of 5GHz. Therefore, it is proposed and implemented a Colpitts oscillator and the corresponding injection-locked oscillator, where as it is proved by the simulations as much as by the experimental results, can function as a divide-by-2 injection-locked frequency divider. From the results that resulted from the measurement of implemented injection-locked oscillator, it becomes clear that the phase noise is obviously improved, as it was expected due to the application of the injection signal. Finally, a differential oscillator was designed and simulated, from which with suitable modification of its topology, resulted a divide-by-2 injection-locked frequency divider. This particular circuit is used widely for the operation of division by-2, because its topology provides a natural divide-by-2 injection point.

In this dissertation, the development of the first 60 GHz-standard compatible fully integrated 4-channel phase-locked loop (PLL) frequency synthesizer has been presented. The frequency synthesizer features third-order single loop architecture with completely integrated passive loop filter that does not require any additional external passive component. Two possible realizations of fully integrated clock and data recovery (CDR) circuits suitable for 60 GHz-standard compliant base band signal processing have been presented for the first time as well. The two CDRs have been optimized for either high data rate (3.456 Gb/s) or very low power consumption (5 mW) and they both work with a single 1 V supply. The frequency synthesizer is intended to generate a variable LO frequency in a fixed-IF heterodyne transceiver architecture. In such configuration the channel selection is implemented by changing the LO frequency by the required frequency step. This method avoids quadrature 50 GHz up/down-conversion thereby lowering the LO mixer design complexity and simplifying the LO distribution network. The measurement results show the PLL locking correctly on each of the four channels while consuming 60 mW from a 1 V power supply. The worst case phase noise is measured to be -80.1 dBc/Hz at 1 MHz offset from the highest frequency carrier (56.16 GHz). The output spectrum shows a reference spur attenuation of -32 dBc. The high data rate CDR features a maximum operating data rate in excess of 3.456 Gb/s while consuming 30 mW of power. The low power CDR consumes only 5 mW and operates at a maximum data rate of 1.728 Gb/s. Over a 1.5 m 60 GHz wireless link, both CDRs allow 95% reduction of the pulse shaping generated input peak-to-peak jitter from 450 ps down to 50 ps.

Ο στόχος της διπλωματικής αυτής εργασίας είναι η μελέτη ενός διαφορικού ταλαντωτή Collpits ο οποίος λειτουργεί ως διαιρέτης συχνότητας με έγχυση ρεύματος στην πηγή, χαμηλού θορύβου και διαφορικής εισόδου, ως προς την κατανάλωση και το θόρυβο. Επίσης συγκρίνεται η απόδοσή του σε αυτούς τους τομείς με την απόδοση άλλων τοπολογιών αναλογικών διαιρετών συχνότητας αλλά και ψηφιακών. / The objective of this thesis is to study a Collpits differential oscillator which works as a low noise and differential input, current source injection frequency divider, by taking into account consumption and noise. Also the performance in these areas is compared with other topologies of analogue and/or digital frequency dividers.

This study presents a novel frequency modulated continuous wave (FMCW) radar system based on sub-harmonic generation, where a 24 GHz frequency divider-by-10 is used as an active reflector tag. A practical prototype is designed and fabricated on a GF45nm-Silicon on Insulator (SOI) technology for the 24 GHz building blocks, while a GF0.18 μm 7WL Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology was used for the 2.4 GHz receiver and baseband. System measurement results show that as opposed to conventional primary radars, the proposed system is immune to strong multi-path interferences resulting from direct reflections of the interrogating signal. The system achieves a ranging precision of 3.7 mm with loop measurements. Moreover, when measured in an indoor environment, the ranging results show a ranging precision and accuracy of 5.8 and 22.3 cm, respectively, which outperform other FMCW radars in the literature.

The design of a 24 GHz frequency divider-by-10 for accurate indoor localisation systems is presented. It is proposed to use frequency dividers as active reflector tags in a frequency-modulated continuous wave indoor localisation system in order to reduce interferences caused by direct reflections of the interrogating signal. Since frequency dividers are subharmonic generators, this allows achieving conversion gain in the reflected signal. The frequency divider is fabricated using GLOBAL FOUNDRIES 45 nm-silicon-on-insulator technology. It consumes only 5.7 mW from a 1 V supply. It has a wide locking range of 33% and an efficiency of 3.58 GHz/mW. To the best of authors' knowledge, the use of frequency dividers as active reflectors was not studied before.