Since the development of deep level transient spectroscopy (DLTS) in the 1970’s by Lang and others, the technique has become a powerful analytical tool to characterise the electrical properties of defects in semiconductors. With the development of more powerful computers and improved data acquisition systems, it has become possible to replace the original analogue boxcar analysers and lock-in amplifiers that were commonly used in early DLTS systems with digitisers and digital signal processing equipment. The use of a computer for signal processing allows for much more flexibility in the DLTS system. For instance, a digital DLTS system is capable of measuring a much wider range of emission rates than an analogue system. Furthermore, since the digital DLTS system does not rely on a repetitive signal, such a system can observe phenomena such as defect metastability that cannot be observed in an analogue system. In this thesis, the design and characterisation of a digital DLTS system is described. The results of a number of experiments that illustrated the capabilities of the system are reported. The extended range of emission rates that could be measured by the system were illustrated by the measuring of the EL2 defect in GaAs over the temperature range 270 – 380 K (corresponding to emission rates ranging from less than 10–3 s–1 to more than 103 s–1). The results compared well with previous results obtained by means of an analogue DLTS system. Further low temperature measurements on the E2 defect in GaAs showed that in the low temperature region, thermal radiation from the cryostat shroud influenced carrier emission. The field dependence of the emission rate of a number of defects, including defects in as-grown n-GaN, He-ion irradiated n-GaN and Si, was investigated as well. The ability of the digital DLTS system to measure single transients was used to investigate configurationally bistable defects in He-ion irradiated p-Si and a sputter-induced defect with negative-U properties in n-GaN. In both of these cases, the results proved far superior to those obtained by means of an analogue system. / Thesis (PhD (Physics))--University of Pretoria, 2007. / Physics / unrestricted

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Electrostatic Discharge (ESD) phenomenon is a common phenomenon in daily life and it could damage the integrated circuit throughout the whole cycle of product from the manufacturing. Several ESD stress models and test methods have been used to reproduce ESD events and characterize ESD protection device's performance. The basic ESD stress models are: Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM). On-chip ESD protection devices are widely used to discharge ESD current and limit the overstress voltage under different ESD events. Some effective ESD protection devices were reported for low speed circuit applications such as analog ICs or digital ICs in CMOS process. On the contrast, only a few ESD protection devices available for radio frequency integrated circuits (RF ICs). ESD protection for RF ICs is more challenging than traditional low speed CMOS ESD protection design because of the facts that: (1) Process limitation: High-performance RF ICs are typically fabricated in compound semiconductor process such as GaAs pHEMT and SiGe HBT process. And some proved effective ESD devices (e.g. SCR) are not able to be fabricated in those processes due to process limitation. Moreover, compound semiconductor process has lower thermal conductivity which will worsen its ESD damage immunity. (2) Parasitic capacitance limitation: Even for RF CMOS process, the inherent parasitic capacitance of ESD protection devices is a big concern. Therefore, this dissertation will contribute on ESD protection designs for RF ICs in all the major processes including GaAs pHEMT, SiGe BiCMOS and standard CMOS. iv The ESD protection for RF ICs in GaAs pHEMT process is very difficult, and the typical HBM protection level is below 1-kV HBM level. The first part of our work is to analyze pHEMT's snapback, post-snapback saturation and thermal failure under ESD stress using TLP-like Sentaurus TCAD simulation. The snapback is caused by virtual bipolar transistor due to large electron-hole pairs impacted near drain region. Postsnapback saturation is caused by temperature-induced mobility degradation due to IIIV compound semiconductor materials' poor thermal conductivity. And thermal failure is found to be caused by hot spot located in pHEMT's InGaAs layer. Understanding of these physical mechanisms is critical to design effective ESD protection device in GaAs pHEMT process. Several novel ESD protection devices were designed in 0.5um GaAs pHEMT process. The multi-gate pHEMT based ESD protection devices in both enhancementmode and depletion-mode were reported and characterized then. Due to the multiple current paths available in the multi-gate pHEMT, the new ESD protection clamp showed significantly improved ESD performances over the conventional single-gate pHEMT ESD clamp, including higher current discharge capability, lower on-state resistance, and smaller voltage transient. We proposed another further enhanced ESD protection clamp based on a novel drain-less, multi-gate pHEMT in a 0.5um GaAs pHEMT technology. Based on Barth 4002 TLP measurement results, the ESD protection devices proposed in this chapter can improve the ESD level from 1-kV (0.6 A It2) to up to 8-kV ( > 5.2 A It2) under HBM. v Then we optimized SiGe-based silicon controlled rectifiers (SiGe SCR) in SiGe BiCMOS process. SiGe SCR is considered a good candidate ESD protection device in this process. But the possible slow turn-on issue under CDM ESD events is the major concern. In order to optimize the turn-on performance of SiGe SCR against CDM ESD, the Barth 4012 very fast TLP (vfTLP) and vfTLP-like TCAD simulation were used for characterization and analysis. It was demonstrated that a SiGe SCR implemented with a P PLUG layer and minimal PNP base width can supply the smallest peak voltage and fastest response time which is resulted from the fact that the impact ionization region and effective base width in the SiGe SCR were reduced due to the presence of the P PLUG layer. This work demonstrated a practical approach for designing optimum ESD protection solutions for the low-voltage/radio frequency integrated circuits in SiGe BiCMOS process. In the end, we optimized SCRs in standard silicon-based CMOS process to supply protection for high speed/radio-frequency ICs. SCR is again considered the best for its excellent current handling ability. But the parasitic capacitance of SCRs needs to be reduced to limit SCR's impact to RF performance. We proposed a novel SCR-based ESD structure and characterize it experimentally for the design of effective ESD protection in high-frequency CMOS based integrated circuits. The proposed SCR-based ESD protection device showed a much lower parasitic capacitance and better ESD performance than the conventional SCR and a low-capacitance SCR reported in the literature. The physics underlying the low capacitance was explained by measurements using HP 4284 capacitance meter. vi Throughout the dissertation work, all the measurements are mainly conducted using Barth 4002 transimission line pulsing (TLP) and Barth 4012 very fast transmission line pulsing (vfTLP) testers. All the simulation was performed using Sentaurus TCAD tool from Synopsys.

Pages 10, 46, 126, 142 and 146 have been omitted because they were completely blank. / <p> This thesis describes the development of a tunable, ultrashort-pulse semiconductor-based laser system operating in the 1 μm wavelength region. The design of the oscillator is based on a two-contact long-wavelength InGaAs-GaAs quantum-well semiconductor device containing integrated gain and saturable absorber sections. A key design component of the oscillator is the fabrication of a curved ridge-waveguide in the gain section of the device, which allows the laser to be operated in a compact, linear external cavity. Under conditions of passive or hybrid mode-locking, the semiconductor oscillator can generate pulses of 1 to 10 ps in duration, which are tunable from 1030 to 1090 nm. The oscillator is also capable of being passively mode-locked at harmonics of the cavity round-trip frequency, allowing tuning of the pulse repetition rate from 0.5 to over 5 GHz. Noise measurements on two independently hybridly mode-locked semiconductor lasers reveal that the absolute noise of each laser is dominated by phase noise at frequencies below 10^5 Hz, while amplitude noise dominates at higher frequencies.</p> <p>Semiconductor and fibre optical amplifiers are used to scale the average power level of the mode-locked pulses. Semiconductor optical amplifiers consisting of narrow-stripe and flared-waveguide designs have been fabricated using the same material structure as that of the mode-locked semiconductor oscillator. Narrow-stripe devices with a length of 800 μm have produced amplified average signal powers of 13 mW, while 1700-μm-long, 2° flared-waveguide devices have produced amplified average signal powers of 50 mW. A fibre-based system consisting of a single-mode double-clad Yb-doped fibre has been constructed to investigate the suitability of a mode-locked diode laser as a seed-source for a Yb:fibre amplifier. Amplified average signal powers of up to 1.4 W have been obtained at the output of the fibre for a launched pump power of 2.1 W. Compression of the amplified pulses using a modified dual-grating compressor yields pulse durations as low as 500 fs and a peak power of up to 1.5 kW.</p> <p> Preliminary work is reported on the development of a novel dual-wavelength optical source consisting of two synchronized mode-locked diode lasers and a polarization-maintaining Yb:fibre amplifier. Numerical simulations based on a rate-equation model for the amplifier gain are conducted to investigate the performance characteristics of a Yb:fibre amplifier when operated under dual-wavelength signal amplification. The simulations are used to predict and optimize the performance of the fibre amplifier for two mode-locked semiconductor-seed-oscillators operating at wavelengths of 1040 and 1079 nm. Good agreement is obtained between the simulations and experimental results. </p> / Thesis / Doctor of Philosophy (PhD)

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<p> In the current research, use of p-n junction GaAs nanowires (NWs) grown by gas source molecular beam epitaxy on GaAs (111) B substrates for the fabrication of flexible solar cells are reported. The solar cells were fabricated by embedding the NWs in a polymer matrix (SU8 2), followed by ohmic contact formation to the tops of the NWs as well as the rear side of the substrate. I-V characteristic curves were obtained by illuminating the solar cells using a solar simulator, indicating a photovoltaic effect. NWs were also detached from the substrate by different methods and successfully transferred onto a flexible substrate for potential use as solar cells. Scanning electron microscopy was used throughout the research for characterization and optimization of the fabrication processes including NW embedment, removal from the substrate, and contact formation.</p> / Thesis / Master of Applied Science (MASc)