In radiation therapy, a treatment plan is designed to make the delivery of radiation to a target more accurate, effective, and less damaging to surrounding healthy tissues. In lung sites, the tumor is affected by the patient’s respiratory motion. Despite tumor motion, current practice still uses a static delivery plan. Unexpected changes due to coughs and sneezes are not taken into account and as a result, the tumor is not treated accurately and healthy tissues are damaged. In this thesis we detail a framework of using an accelerometer device to detect and forecast coughs. The accelerometer measurements are modeled as a ARMA process to make forecasts. We draw from studies in cough physiology and use amplitudes and durations of the forecasted breathing cycles as features to estimate parameters of Gaussian Mixture Models for cough and normal breathing classes. The system was tested on 10 volunteers, where each data set consisted of one 3-5 minute accelerometer measurements to train the system, and two 1-3 minute accelerometer measurements for testing.

Phase-contrast magnetic resonance imaging (PC-MRI) can provide a complement to echocardiography for the evaluation of the fetal heart. Cardiac imaging typically requires gating with peripheral hardware; however, a gating signal is not readily available in utero. In this thesis, I present a technique for reconstructing time-resolved fetal phase-contrast MRI in spite of this limitation. Metric Optimized Gating (MOG) involves acquiring data without gating and retrospectively determining the proper reconstruction by optimizing an image metric, and the research in this thesis describes the theory, implementation, and evaluation of this technique. In particular, results from an experiment with a pulsatile flow phantom, an adult volunteer study, in vivo application in the fetal population, and numerical simulations are presented for validation. MOG enables imaging with conventional PC-MRI sequences in the absence of a gating signal, permitting flow measurements in the great vessels in utero.

The recent determination of several crystal structures of voltage-gated ion channels has catalyzed computational efforts of studying these remarkable molecular machines that are able to conduct ions across biological membranes at extremely high rates without compromising the ion selectivity. Starting from the open crystal structures, we have studied the gating mechanism of these channels by molecular modeling techniques. Firstly, by applying a membrane potential, initial stages of the closing of the channel were captured, manifested in a secondary-structure change in the voltage-sensor. In a follow-up study, we found that the energetic cost of translocating this 310-helix conformation was significantly lower than in the original conformation. Thirdly, collaborators of ours identified new molecular constraints for different states along the gating pathway. We used those to build new protein models that were evaluated by simulations. All these results point to a gating mechanism where the S4 helix undergoes a secondary structure transformation during gating. These simulations also provide information about how the protein interacts with the surrounding membrane. In particular, we found that lipid molecules close to the protein diffuse together with it, forming a large dynamic lipid-protein cluster. This has important consequences for the understanding of protein-membrane interactions and for the theories of lateral diffusion of membrane proteins. Further, simulations of the simple ion channel antiamoebin were performed where different molecular models of the channel were evaluated by calculating ion conduction rates, which were compared to experimentally measured values. One of the models had a conductance consistent with the experimental data and was proposed to represent the biological active state of the channel. Finally, the underlying methods for simulating molecular systems were probed by implementing the CHARMM force field into the GROMACS simulation package. The implementation was verified and specific GROMACS-features were combined with CHARMM and evaluated on long timescales. The CHARMM interaction potential was found to sample relevant protein conformations indifferently of the model of solvent used. / At the time of the doctoral defense, the following paper was unpublished and had a status as follows: Paper 3: Manuscript.

Dissertation (Ph.D.)--University of South Florida, 2005. / Includes vita. Includes bibliographical references. Also available online as a PDF document.

Thesis (Ph. D.)--University of Missouri--Columbia, 1998. / "December 1998" Typescript. Vita. Includes bibliographical references (l. 140-148). Also available on the Internet.

Thesis (Ph.D.)--Indiana University, 2010. / Title from screen (viewed on April 1, 2010). Department of Pharmacology and Toxicology, Indiana University-Purdue University Indianapolis (IUPUI). Advisor(s): Theodore R. Cummins, Grant D. Nicol, Gerry S. Oxford, Andy Hudmon, John H. Schild. Includes vitae. Includes bibliographical references (leaves 232-266).

Thesis (Ph. D.)--University of Washington, 1999. / Vita. Includes bibliographical references (leaves 68-82).

Thesis (Ph. D.) -- University of Texas Southwestern Medical Center at Dallas, 2006. / Embargoed. Vita. Bibliography: 134-139.

Nesse trabalho é apresentada uma arquitetura que habilita a geração de MPSoCs (Multiprocessors Systems-on-Chip) heterogêneos escaláveis, baseados em barramento, suportando ainda o uso de diferentes organizações de memória. A comunicação entre as tarefas é especificada por meio de uma estrutura de memória compartilhada, que evita colisões e promove ganhos energéticos através do disparo dinâmico de clock gating. Também é introduzida a técnica DCF (Dynamic Core Freezing), que incrementa a eficiência energética do MPSoC tirando proveito dos ciclos ociosos dos processadores durante os acessos à memória. Mais, a combinação das organizações de memória propostas habilita a exploração de migração de tarefas na arquitetura proposta, por meio da troca de contexto das tarefas na memória compartilhada. Além disso, é mostrado o simulador de alto-nível, baseado na arquitetura proposta, criado com o propósito de extrair os ganhos energéticos propiciados com o uso do clock gating e da técnica DCF. O simulador aceita como entrada arquivos de trace de execução de aplicações Java, com os quais ele gera um novo arquivo contendo o mapeamento das instruções encontradas nos arquivos de trace para diferentes classes de instrução. Dessa forma, podem ser modeladas diferentes arquiteturas de processadores, usando o arquivo com o mapeamento para simular o MPSoC. Mais, o simulador habilita ainda a exploração das diferentes organizações de memória da arquitetura proposta, de maneira que se pode estimar o seu impacto no número de instruções executadas, contenções no barramento, e consumo energético. Experimentos baseados em uma aplicação sintética, executando em um MPSoC composto por diferentes versões de um processador Java mostram um grande aumento na eficiência energética com um custo mínimo em área. Além disso, também são apresentados experimentos baseados em aplicações do benchmark SPECjvm98, que mostram o impacto causado na eficiência energética quando o tipo de aplicação é alterado. Mais, os experimentos mostram drásticos ganhos energéticos obtidos com a aplicação da técnica DCF sobre as memórias do MPSoC. / In this work we present an architecture that enables the generation of bus-based, scalable heterogeneous Multiprocessor Systems-on-Chip (MPSoCs), supporting different memory organizations. Intertask communication is specified by means of a shared memory structure that assures collision avoidance and promotes energy savings through a dynamic clock gating triggering. We also introduce a Dynamic Core Freezing (DCF) technique, which boosts energy savings taking advantage of processor idle cycles during memory accesses. Moreover, the combination of the memory organizations enables the architecture to exploit easy task migration by means of the task context saving in the shared data memory. Moreover, we show the high-level simulator, based on the proposed architecture, created in order to extract the energy savings enabled with the clock gating and the DCF techniques. The simulator accepts as input execution trace files of Java applications, from which it generates a new file that contains the mapping of the instructions found in the trace file for different instruction classes. This way, we can model different processor architectures, using the mapping file to simulate the MPSoC. Also, the simulator enables us to experiment with different memory organizations to estimate their impact on the executed instructions, bus contention, and energy consumption. As case study we have modeled different versions of a Java processor in order to experiment with different execution patterns over different memory organizations. Experiments based on a synthetic application running on an MPSoC containing different versions of a Java processor show a large improvement in energy efficiency with a minimal area cost. Besides that, we also present experiments based on applications of the SPECjvm98 benchmark, which show the impact on the energy efficiency when we change the application type. Moreover, the experiments show a huge improvement in the energy efficiency when applying the DCF technique to the MPSoC memories.

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperformance ) para SAD, em baixa frequência, alto paralelismo e, principalmente, com um estágio de pipeline. Além disso, tecnologias CMOS mais avançadas diminuem o consumo de potência dinâmica e, em alguns casos, também diminuem a potência estática por gate equivalente, se utilizadas células High-VT e tensão de alimentação a menor possível. Outro fator a ser destacado é o uso do clock gating que no caso das arquiteturas de SAD, em vez de diminuir, aumenta o consumo de potência dinâmica. Neste trabalho foi realizada a síntese do decodificador Intra-Only. O decodificador com clock gating apresenta um menor consumo de potência, mostrando um caso em que esta técnica é benéfica. Além disso, a utilização de uma tecnologia CMOS 65 nm e, consequentemente, tensão de alimentação menor, levou a uma sensível diminuição no consumo de potência em relação a outros trabalhos similares. / This work presents low-power techniques applications to digital blocks in the SAD algorithm and in the Intra-Only H.264/AVC decoder. In the hardware description, we add parallelism and pipeline techniques. In the logical and physical synthesis exploration, includes the clock gating, multiple threshold voltage, different technologies and multiple supply voltage. The synthesis are done in the CadenceTM tools and show a smaller energy per operation in isoperformance for SAD at low frequency, high parallelism and, mainly, with one pipeline stage. In addition to that, more advanced CMOS technologies decrease the dynamic power consumption and, also, decrease the static power for equivalent gates, if using High-VT cells and lowest possible power supply. Another factor is the clock gating use that in the SAD architecture, instead of decreasing, increases the dynamic power consumption. In this work the design of an Intra-Only H.264/AVC Decoder was performed. This design with clock gating presents lower power consumption, showing a case in which this technique is beneficial in terms of dynamic power. Besides that, the 65 nm CMOS technology uses a lower power supply, resulting in lower power consumption in comparison to other related works.