Nesse trabalho é apresentada uma arquitetura que habilita a geração de MPSoCs (Multiprocessors Systems-on-Chip) heterogêneos escaláveis, baseados em barramento, suportando ainda o uso de diferentes organizações de memória. A comunicação entre as tarefas é especificada por meio de uma estrutura de memória compartilhada, que evita colisões e promove ganhos energéticos através do disparo dinâmico de clock gating. Também é introduzida a técnica DCF (Dynamic Core Freezing), que incrementa a eficiência energética do MPSoC tirando proveito dos ciclos ociosos dos processadores durante os acessos à memória. Mais, a combinação das organizações de memória propostas habilita a exploração de migração de tarefas na arquitetura proposta, por meio da troca de contexto das tarefas na memória compartilhada. Além disso, é mostrado o simulador de alto-nível, baseado na arquitetura proposta, criado com o propósito de extrair os ganhos energéticos propiciados com o uso do clock gating e da técnica DCF. O simulador aceita como entrada arquivos de trace de execução de aplicações Java, com os quais ele gera um novo arquivo contendo o mapeamento das instruções encontradas nos arquivos de trace para diferentes classes de instrução. Dessa forma, podem ser modeladas diferentes arquiteturas de processadores, usando o arquivo com o mapeamento para simular o MPSoC. Mais, o simulador habilita ainda a exploração das diferentes organizações de memória da arquitetura proposta, de maneira que se pode estimar o seu impacto no número de instruções executadas, contenções no barramento, e consumo energético. Experimentos baseados em uma aplicação sintética, executando em um MPSoC composto por diferentes versões de um processador Java mostram um grande aumento na eficiência energética com um custo mínimo em área. Além disso, também são apresentados experimentos baseados em aplicações do benchmark SPECjvm98, que mostram o impacto causado na eficiência energética quando o tipo de aplicação é alterado. Mais, os experimentos mostram drásticos ganhos energéticos obtidos com a aplicação da técnica DCF sobre as memórias do MPSoC. / In this work we present an architecture that enables the generation of bus-based, scalable heterogeneous Multiprocessor Systems-on-Chip (MPSoCs), supporting different memory organizations. Intertask communication is specified by means of a shared memory structure that assures collision avoidance and promotes energy savings through a dynamic clock gating triggering. We also introduce a Dynamic Core Freezing (DCF) technique, which boosts energy savings taking advantage of processor idle cycles during memory accesses. Moreover, the combination of the memory organizations enables the architecture to exploit easy task migration by means of the task context saving in the shared data memory. Moreover, we show the high-level simulator, based on the proposed architecture, created in order to extract the energy savings enabled with the clock gating and the DCF techniques. The simulator accepts as input execution trace files of Java applications, from which it generates a new file that contains the mapping of the instructions found in the trace file for different instruction classes. This way, we can model different processor architectures, using the mapping file to simulate the MPSoC. Also, the simulator enables us to experiment with different memory organizations to estimate their impact on the executed instructions, bus contention, and energy consumption. As case study we have modeled different versions of a Java processor in order to experiment with different execution patterns over different memory organizations. Experiments based on a synthetic application running on an MPSoC containing different versions of a Java processor show a large improvement in energy efficiency with a minimal area cost. Besides that, we also present experiments based on applications of the SPECjvm98 benchmark, which show the impact on the energy efficiency when we change the application type. Moreover, the experiments show a huge improvement in the energy efficiency when applying the DCF technique to the MPSoC memories.

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperformance ) para SAD, em baixa frequência, alto paralelismo e, principalmente, com um estágio de pipeline. Além disso, tecnologias CMOS mais avançadas diminuem o consumo de potência dinâmica e, em alguns casos, também diminuem a potência estática por gate equivalente, se utilizadas células High-VT e tensão de alimentação a menor possível. Outro fator a ser destacado é o uso do clock gating que no caso das arquiteturas de SAD, em vez de diminuir, aumenta o consumo de potência dinâmica. Neste trabalho foi realizada a síntese do decodificador Intra-Only. O decodificador com clock gating apresenta um menor consumo de potência, mostrando um caso em que esta técnica é benéfica. Além disso, a utilização de uma tecnologia CMOS 65 nm e, consequentemente, tensão de alimentação menor, levou a uma sensível diminuição no consumo de potência em relação a outros trabalhos similares. / This work presents low-power techniques applications to digital blocks in the SAD algorithm and in the Intra-Only H.264/AVC decoder. In the hardware description, we add parallelism and pipeline techniques. In the logical and physical synthesis exploration, includes the clock gating, multiple threshold voltage, different technologies and multiple supply voltage. The synthesis are done in the CadenceTM tools and show a smaller energy per operation in isoperformance for SAD at low frequency, high parallelism and, mainly, with one pipeline stage. In addition to that, more advanced CMOS technologies decrease the dynamic power consumption and, also, decrease the static power for equivalent gates, if using High-VT cells and lowest possible power supply. Another factor is the clock gating use that in the SAD architecture, instead of decreasing, increases the dynamic power consumption. In this work the design of an Intra-Only H.264/AVC Decoder was performed. This design with clock gating presents lower power consumption, showing a case in which this technique is beneficial in terms of dynamic power. Besides that, the 65 nm CMOS technology uses a lower power supply, resulting in lower power consumption in comparison to other related works.

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperformance ) para SAD, em baixa frequência, alto paralelismo e, principalmente, com um estágio de pipeline. Além disso, tecnologias CMOS mais avançadas diminuem o consumo de potência dinâmica e, em alguns casos, também diminuem a potência estática por gate equivalente, se utilizadas células High-VT e tensão de alimentação a menor possível. Outro fator a ser destacado é o uso do clock gating que no caso das arquiteturas de SAD, em vez de diminuir, aumenta o consumo de potência dinâmica. Neste trabalho foi realizada a síntese do decodificador Intra-Only. O decodificador com clock gating apresenta um menor consumo de potência, mostrando um caso em que esta técnica é benéfica. Além disso, a utilização de uma tecnologia CMOS 65 nm e, consequentemente, tensão de alimentação menor, levou a uma sensível diminuição no consumo de potência em relação a outros trabalhos similares. / This work presents low-power techniques applications to digital blocks in the SAD algorithm and in the Intra-Only H.264/AVC decoder. In the hardware description, we add parallelism and pipeline techniques. In the logical and physical synthesis exploration, includes the clock gating, multiple threshold voltage, different technologies and multiple supply voltage. The synthesis are done in the CadenceTM tools and show a smaller energy per operation in isoperformance for SAD at low frequency, high parallelism and, mainly, with one pipeline stage. In addition to that, more advanced CMOS technologies decrease the dynamic power consumption and, also, decrease the static power for equivalent gates, if using High-VT cells and lowest possible power supply. Another factor is the clock gating use that in the SAD architecture, instead of decreasing, increases the dynamic power consumption. In this work the design of an Intra-Only H.264/AVC Decoder was performed. This design with clock gating presents lower power consumption, showing a case in which this technique is beneficial in terms of dynamic power. Besides that, the 65 nm CMOS technology uses a lower power supply, resulting in lower power consumption in comparison to other related works.

Doctor of Philosophy / Department of Physics / Zenghu Chang / It is still a dream to image the dynamics of electrons in atoms and molecules experimentally. This is due to the fact that such motion takes place in an ultra-short time scale; for example, an electron moves around the Bohr orbit in about 150-as (1 as = 10 -18 s), and pulses much shorter than this limit are not currently available to probe such fast dynamics. In recent years, an isolated single attosecond pulse has been produced by extracting the cutoff of harmonic spectrum driven by a laser pulse as short as ~ 5fs (1fs =10-15 s). But, these pulses are still too long in order to make the dream come true. Here, we study the possibility of generation of a much shorter and wavelength tunable single attosecond pulse by using polarization gating. In the experiment, we compressed ~30fs pulses from the laser amplifier down to ~6fs and characterized them. These linearly polarized pulses were converted to ellipticity varying pulses, and by exploiting the property of the strong dependence of the harmonic signal with the ellipticity of the laser, an XUV supercontinuum was produced in the harmonic spectrum which could support 60-as pulses. The bandwidth of such a supercontinuum, and therefore the duration of the attosecond pulses, is limited mainly by the currently available energy of the driving laser pulses at few cycle limits. In this project, we present an approach which allowed us to scale up the energy of such pulses by a factor of 1.5 in “Hollow Core Fiber / Chirped Mirrors Compressor”. Finally, in order to temporarily characterize the attosecond pulses we designed and built an “Attosecond Streak Camera”. Most of such cameras to date are limited to measuring a 1 dimensional energy spectrum and have only a few degrees of acceptance angle. Our camera is capable of measuring 2d momentum of the photoelectrons with large acceptance angle, for example ~ 65o at the photoelectron of energy ~15 eV. Recently, we observed the sidebands in addition to the main peaks in their laser assisted XUV photoelectron spectrum. The single attosecond pulses, after being characterized with this high speed camera, can be used to explore the dynamics of electrons at the attosecond scale.

A study was done at Steve Biko Academic hospital to determine the influence that respiratory gating will have on target volumes used in radiotherapy treatment planning. The primary objective was to compare target volumes of respiratory gated scans to ungated scans and to determine whether it will be meaningful to permanently implement a 4D respiratory gating system on CT scanners in the South African public health sector and to use these images for target volume delineation in radiotherapy planning. The study consisted of three sections. In the first section, 4D respiratory gated CT images were obtained and delineated with 4D software. The full-inspiration and full-expiration phases of the gated scans were then fused to obtain ungated images which were also delineated. The gross tumor volumes (GTVs) of the gated phases were compared to the ungated GTVs, and found that on average the volumes decreased by 14.63% with a standard deviation of 7.96% when gating was applied. Yet another aim was to determine the influence that 4D imaging will have on radiotherapy treatment planning. One of the 4D study sets was imported to the XIO treatment planning system where IMRT treatment plans were created on both the gated and ungated scans. The plans conformed to the treatment aims and restrictions when clinical parameters such as DVHs were used to evaluate it. The planned target volume coverage differed by less than 1% between the gated and the ungated plans, but significant dose reductions to the OARs of up to 32.65% to the contralateral lung were recorded on the gated plan. In the second section of this study, respiratory gated CT scans were simulated by applying the breath-hold technique to lung cancer patients. The technique was applied during full-inspiration which fundamentally represents the maximum peak of the sinusoidal respiratory waveform. An ungated scan was also acquired during normal respiration. The clinical target volumes (CTVs) were identified on both scans by three oncologists and the average CTVs were compared. It was found that the CTVs decreased significantly by an average of 14.33%. Palliative patients receive parallel opposing field therapy which is planned from 2D films. It is very unlikely that these opposing field sizes will differ when gating is applied. It was therefore concluded that only radical lung patients, which was estimated to be a mere 0.03% of the total radiation therapy patient population, will benefit by implementing respiratory gating or any motion-reduction technique. For the third section of the study, respiratory gated PET scans were acquired on a PET/CT scanner to evaluate external, non-technical parameters that will influence respiratory gating. The results indicated that time and patient participation were not limiting factors. The biggest concerns however were the effectiveness of the gating system, software limitations and the gated results. These problems might be minimized with thorough training on the system. All three sections as well as the financial implications were considered to conclude that it will not be meaningful to implement 4D respiratory gating techniques in the South African public health sector Copyright / Dissertation (MSc)--University of Pretoria, 2013. / Medical Oncology / unrestricted

Nowadays, thanks to the continuous improvements in the integration scale, more and more cores are added on the same chip, leading to higher system performance. In order to interconnect all nodes, a network-on-chip (NoC) is used, which is in charge of delivering data between cores. However, increasing the number of cores leads to a significant power consumption increase, leading the NoC to be one of the most expensive components in terms of power. Because of this, during the last years, several mechanisms have been proposed to address the NoC power consumption by means of DVFS (Dynamic Voltage and Frequency Scaling) and power-gating strategies. Nevertheless, improvements achieved by these mechanisms are achieved, to a greater or lesser extent, at the cost of system performance, potentially increasing the risk of saturating the network by forming congested points which, in turn, compromise the rest of the system functionality. One side effect is the creation of the "Head-of-Line blocking" effect where congested packets at the head of queues prevent other non-blocked packets from advancing. To address this issue, in this thesis, on one hand, we propose novel congestion control techniques in order to improve system performance by removing the "Head-of-Line" blocking effect. On the other hand, we propose combined solutions adapted to DVFS in order to achieve improvements in terms of performance and power. In addition to this, we propose a path-aware power-gating-based mechanism, which is capable of detecting the flows sharing buffer resources along data paths and perform to switch them off when not needed. With all these combined solutions we can significantly reduce the power consumption of the NoC when compared with state-of-the-art proposals. / Hoy en día, gracias a las mejoras en la escala de integración cada vez se integran más y más núcleos en un mismo chip, mejorando así sus prestaciones. Para interconectar todos los nodos dentro del chip se emplea una red en chip (NoC, Network-on-Chip), la cual es la encargada de intercambiar información entre núcleos. No obstante, aumentar el número de núcleos en el chip también conlleva a su vez un importante incremento en el consumo de la NoC, haciendo que ésta se convierta en una de las partes más caras del chip en términos de consumo. Por ello, en los últimos años se han propuesto diversas técnicas de ahorro de energía orientadas a reducir el consumo de la NoC mediante el uso de DVFS (Dynamic Voltage and Frequency Scaling) o estrategias basadas en "power-gating". Sin embargo, éstas mejoras de consumo normalmente se obtienen a costa de sacrificar, en mayor o menor medida, las prestaciones del sistema, aumentado potencialmente así el riesgo de saturar la red, generando puntos de congestión que, a su vez, comprometen el rendimiento del resto del sistema. Un efecto colateral es el "Head-of-Line blocking", mediante el que paquetes congestionados en la cabeza de la cola impiden que otros paquetes no congestionados avancen. Con el fin de solucionar este problema, en ésta tesis, en primer lugar, proponemos técnicas novedosas de control de congestión para incrementar el rendimiento del sistema mediante la eliminación del "Head-of-Line blocking", mientras que, por otra parte, proponemos soluciones combinadas adaptadas a DVFS con el fin de conseguir mejoras en términos de rendimiento y energía. Además, proponemos una técnica de "power-gating" orientada a rutas de datos, la cual es capaz de detectar flujos de datos compartiendo recursos a lo largo de rutas y apagar dichos recursos de forma dinámica cuando no son necesarios. Con todas éstas soluciones combinadas podemos reducir el consumo de energía de la NoC en comparación con otras técnicas presentes en el estado del arte. / Hui en dia, gr\`acies a les millores en l'escala d'integraci\'o, cada vegada s'integren m\'es i m\'es nuclis en un mateix xip, la qual cosa millora les seues prestacions. Per tal d'interconectar tots els nodes dins el xip es fa \'us d'una Xarxa en Xip (NoC; Network-on-Chip), la qual \'es l'encarregada d'intercanviar informaci\'o entre els nuclis. No obstant aix\`o, incrementar el nombre de nuclis en el xip tamb\'e comporta un important augment en el consum de la NoC, la qual cosa fa que aquesta es convertisca en una de les parts m\'es costoses del xip en termes de consum. Per aix\`o, en els \'ultims anys s'han proposat diverses t\`ecniques d'estalvi d'energia orientades a reduir el consum de la NoC mitjançant l'\'us de DVFS (Dynamic Voltage and Frequency Scaling) o estrat\`egies basades en ``power-gating''. Malgrat aix\`o, aquestes millores en les prestacions normalment s'obtenen a costa de sacrificar, en major o menor mesura, les prestacions del sistema i augmenta aix\'i el risc de saturar la xarxa al generar-se punts de congesti\'o, que al mateix temps, comprometen el rendiment de la resta del sistema. Un efecte col-lateral \'es el ``Head-of- Line blocking'', mitjançant el qual, els paquets congestionats al cap de la cua, impedixen que altres paquets no congestionats avancen. A fi de solucionar eixe problema, en aquesta tesi, en primer lloc, proposem noves t\`ecniques de control de congesti\'o amb l'objectiu d'incrementar el rendiment del sistema per mitj\`a de l'eliminaci\'o del ``Head-of- Line blocking'', i d'altra banda, proposem solucions combinades adaptades a DVFS amb la finalitat d'aconseguir millores en termes de rendiment i energia. A m\'es, proposem una t\`ecnica de ``power-gating'' orientada a rutes de dades, la qual \'es capa\c c de detectar fluxos de dades al compartir recursos al llarg de les rutes i apagar eixos recursos de forma din\`amica quan no s\'on necessaris. Amb totes aquestes solucions combinades podem reduir el consum d'energia de la NoC en comparaci\'o amb altres t\`ecniques presents en l'estat de l'art. / Escamilla López, JV. (2017). Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/90419 / TESIS

Developing lifelike vocal fold models is challenging due to various associatedbiomechanical complexities. Nevertheless, the development and analysis of improved vocal foldmodels is worthwhile since they are valuable tools for gaining insight into human vocal foldvibratory, aerodynamic, and acoustic response characteristics. This thesis seeks to contribute tothe development of computational and physical vocal fold modeling in two ways. First is byintroducing a method of obtaining internal deformation fields within vibrating synthetic vocal foldmodels; second is by presenting an optimization algorithm coupled with a computational vocalfold model to optimize geometry and stiffness of a synthetic vocal fold model to achieve morerealistic vibration patterns.The method for tracking the internal deformation of self-oscillating vocal fold models isbased on MR imaging. Silicone models scaled to four times life-size to lower the flow-inducedvibration frequency were imbedded with fiducial markers in a coronal plane. Candidate markermaterials were tested using static specimens, and two materials, cupric sulfate and glass, werechosen for testing in the vibrating VF models. The vibrating models were imaged using a gatedMRI protocol wherein MRI acquisition was triggered using the subglottal pressure signal. Twodimensionalimage slices at different phases during self-oscillation were captured, and in eachphase the fiducial markers were clearly visible. The process was also demonstrated using a threedimensionalscan at two phases. The benefit of averaging to increase signal-to-noise ratio wasexplored. The results demonstrate the ability to use MRI to acquire quantitative deformation datathat could be used, for example, to validate computational models of flow-induced VF vibrationand quantify deformation fields encountered by cells in bioreactor studies.A low fidelity, two-dimensional, finite element model of VF flow-induced vibration wascoupled with a custom MATLAB-based genetic algorithm optimizer. The objective was to achievea closed quotient within the normal human physiological range. The results showed that changesin geometry and stiffness would lead to a model that exhibited the desired characteristics. Aphysical model based on optimized parameters was then fabricated and the closed quotient wastested. The physical model successfully vibrated with nonzero closed quotient as predicted by thecomputational model.

This thesis focuses on cardiac imaging and quantification of T1 relaxation time in rat hearts. Its main focus is to investigate available methods for such quantification and their application in the development of quantification tools. The large impact is given to methods of acquisition synchronization, mainly with respect to cardiac motion and breathing using retrospective gating, where the navigator signal is obtained solely from the acquired data, so without any external equipment such as the ECG or respiratory sensors. This paper takes into account situations where steady-state has been reached and also those where it has not, by means of contrast agent injection or by inversion pulses.

Epigenetics, or alterations in the phenotype or gene expression due to mechanisms other than changes in the underlying DNA sequence, reflects the sensitivity and responsiveness of human and animal brains in constantly varying circumstances regulating gene expression profiles that define the biomarkers and present the ultimate phenotypical outcomes, such as cognition and emotion. Epigenetics is associated with functionally relevant alterations to the genome in such a fashion that under the particular conditions of early, adolescent, and adult life, environmental signals may activate intracellular pathways that remodel the "epigenome," triggering changes in gene expression and neural function. Thus, genetic influences in neuropsychiatric disorders that are subject to clinical staging, epigenetics in schizophrenia, epigenetic considerations in the expression of sensorimotor gating resulting from disease conditions, biomarkers of drug use and addiction, current notions on the role of dopamine in schizophrenia spectrum disorders, and the discrete interactions of biomarkers in persistent memory were to greater or lesser extents reflected upon. The relative contributions of endophenotypes and epistasis for mediating epigenetic phenomena and the outcomes as observed in the analysis of biomarkers appear to offer a multitude of interactive combinations to further complicate the labyrinthine machinations of diagnosis, intervention, and prognosis.

No description available.