The robust popularization of 3D videos noticed along the last decade, allied to the omnipresence of smart mobile devices handling multimedia-capable features, has led to intense development and research focusing on efficient 3D-video encoding techniques, display technologies, and 3D-video capable mobile devices. In this scenario, the Multiview Video Coding (MVC) standard is key enabler of the current 3D-video systems by leading to meaningful data reduction through advanced encoding techniques. However, real-time MVC encoding for high definition videos demands high processing performance and, consequently, high energy consumption. These requirements are attended neither by the performance budget nor by the energy envelope available in the state-of-the-art mobile devices. As a result, the realization of MVC targeting mobile systems has been posing serious challenges to industry and academia. The main goal of this thesis is to propose and demonstrate energy-efficient MVC solutions to enable high-definition 3D-video encoding on mobile battery-powered embedded systems. To expedite high performance under severe energy constraints, this thesis proposes jointly considering energy-efficient optimizations at algorithmic and architectural levels. On the one hand, extensive application knowledge and data analysis was employed to reduce and control the MVC complexity and energy consumption at algorithmic level. On the other hand, hardware architectures specifically designed targeting the proposed algorithms were implemented applying low-power design techniques, dynamic voltage scaling, and application-aware dynamic power management. The algorithmic contribution lies in the MVC energy reduction by shorten the computational complexity of the energy-hungriest encoder blocks, the Mode Decision and the Motion and Disparity Estimation. The proposed energy-efficient algorithms take advantage of the video properties along with the strong correlation available within the 3D-Neighborhood (spatial, temporal and disparity) space in order to efficiently reduce energy consumption. Our Multi-Level Fast Mode Decision defines two complexity reduction operation modes able to provide, on average, 63% and 71% of complexity reduction, respectively. Additionally, the proposed Fast ME/DE algorithm reduces the complexity in about 83%, for the average case. Considering the run-time variations posed by changing coding parameters and video content, an Energy-Aware Complexity Adaptation algorithm is proposed to handle the energy versus coding efficiency tradeoff while providing graceful quality degradation under severe battery draining scenarios by employing asymmetric video coding. Finally, to cope with eventual video quality losses posed by the energy-efficient algorithms, we define a video quality management technique based on our Hierarchical Rate Control. The Hierarchical Rate Control implements a frame-level rate control based on a Model Predictive Controller able to increase in 0.8dB (Bjøntegaard) the overall video quality. The video quality is increased in 1.9dB (Bjøntegaard) with the integration of the basic unit-level rate control designed using Markov Decision Process and Reinforcement Learning. Even though the energy-efficient algorithms drive to meaningful energy reduction, hardware acceleration is mandatory to reach the energy-efficiency demanded by the MVC. Aware of this requirement, this thesis brings architectural solutions for the Motion and Disparity Estimation unit focusing on energy reduction while attending real-time throughput requirements. To achieve the desired results, as shown along this volume, there is a need to reduce the energy related to the ME/DE computation and related to the intense memory communication. Therefore, the ME/DE architectures incorporate the Fast ME/DE algorithm in order to reduce the computational complexity while the memory hierarchy was carefully designed to find the optimal energy tradeoff between external memory accesses and on-chip video memory size. Statistical analysis where used to define the size and organization of the on-chip cache memory while avoiding increased memory misses and the consequent data retransmission. A prefetching technique based on search window prediction also supports the reduction of external memory access. Moreover, a memory power gating technique based on dynamic search window formation and an application aware power management were proposed to reduce the static energy consumption related to on-chip video memory. To implement these techniques a SRAM memory featuring multiple power states was used. The architectural contribution contained in this thesis extends the state-of-the-art by achieving real-time ME/DE processing for 4-views HD1080p running at 300MHz and consuming 57mW.

The robust popularization of 3D videos noticed along the last decade, allied to the omnipresence of smart mobile devices handling multimedia-capable features, has led to intense development and research focusing on efficient 3D-video encoding techniques, display technologies, and 3D-video capable mobile devices. In this scenario, the Multiview Video Coding (MVC) standard is key enabler of the current 3D-video systems by leading to meaningful data reduction through advanced encoding techniques. However, real-time MVC encoding for high definition videos demands high processing performance and, consequently, high energy consumption. These requirements are attended neither by the performance budget nor by the energy envelope available in the state-of-the-art mobile devices. As a result, the realization of MVC targeting mobile systems has been posing serious challenges to industry and academia. The main goal of this thesis is to propose and demonstrate energy-efficient MVC solutions to enable high-definition 3D-video encoding on mobile battery-powered embedded systems. To expedite high performance under severe energy constraints, this thesis proposes jointly considering energy-efficient optimizations at algorithmic and architectural levels. On the one hand, extensive application knowledge and data analysis was employed to reduce and control the MVC complexity and energy consumption at algorithmic level. On the other hand, hardware architectures specifically designed targeting the proposed algorithms were implemented applying low-power design techniques, dynamic voltage scaling, and application-aware dynamic power management. The algorithmic contribution lies in the MVC energy reduction by shorten the computational complexity of the energy-hungriest encoder blocks, the Mode Decision and the Motion and Disparity Estimation. The proposed energy-efficient algorithms take advantage of the video properties along with the strong correlation available within the 3D-Neighborhood (spatial, temporal and disparity) space in order to efficiently reduce energy consumption. Our Multi-Level Fast Mode Decision defines two complexity reduction operation modes able to provide, on average, 63% and 71% of complexity reduction, respectively. Additionally, the proposed Fast ME/DE algorithm reduces the complexity in about 83%, for the average case. Considering the run-time variations posed by changing coding parameters and video content, an Energy-Aware Complexity Adaptation algorithm is proposed to handle the energy versus coding efficiency tradeoff while providing graceful quality degradation under severe battery draining scenarios by employing asymmetric video coding. Finally, to cope with eventual video quality losses posed by the energy-efficient algorithms, we define a video quality management technique based on our Hierarchical Rate Control. The Hierarchical Rate Control implements a frame-level rate control based on a Model Predictive Controller able to increase in 0.8dB (Bjøntegaard) the overall video quality. The video quality is increased in 1.9dB (Bjøntegaard) with the integration of the basic unit-level rate control designed using Markov Decision Process and Reinforcement Learning. Even though the energy-efficient algorithms drive to meaningful energy reduction, hardware acceleration is mandatory to reach the energy-efficiency demanded by the MVC. Aware of this requirement, this thesis brings architectural solutions for the Motion and Disparity Estimation unit focusing on energy reduction while attending real-time throughput requirements. To achieve the desired results, as shown along this volume, there is a need to reduce the energy related to the ME/DE computation and related to the intense memory communication. Therefore, the ME/DE architectures incorporate the Fast ME/DE algorithm in order to reduce the computational complexity while the memory hierarchy was carefully designed to find the optimal energy tradeoff between external memory accesses and on-chip video memory size. Statistical analysis where used to define the size and organization of the on-chip cache memory while avoiding increased memory misses and the consequent data retransmission. A prefetching technique based on search window prediction also supports the reduction of external memory access. Moreover, a memory power gating technique based on dynamic search window formation and an application aware power management were proposed to reduce the static energy consumption related to on-chip video memory. To implement these techniques a SRAM memory featuring multiple power states was used. The architectural contribution contained in this thesis extends the state-of-the-art by achieving real-time ME/DE processing for 4-views HD1080p running at 300MHz and consuming 57mW.

The robust popularization of 3D videos noticed along the last decade, allied to the omnipresence of smart mobile devices handling multimedia-capable features, has led to intense development and research focusing on efficient 3D-video encoding techniques, display technologies, and 3D-video capable mobile devices. In this scenario, the Multiview Video Coding (MVC) standard is key enabler of the current 3D-video systems by leading to meaningful data reduction through advanced encoding techniques. However, real-time MVC encoding for high definition videos demands high processing performance and, consequently, high energy consumption. These requirements are attended neither by the performance budget nor by the energy envelope available in the state-of-the-art mobile devices. As a result, the realization of MVC targeting mobile systems has been posing serious challenges to industry and academia. The main goal of this thesis is to propose and demonstrate energy-efficient MVC solutions to enable high-definition 3D-video encoding on mobile battery-powered embedded systems. To expedite high performance under severe energy constraints, this thesis proposes jointly considering energy-efficient optimizations at algorithmic and architectural levels. On the one hand, extensive application knowledge and data analysis was employed to reduce and control the MVC complexity and energy consumption at algorithmic level. On the other hand, hardware architectures specifically designed targeting the proposed algorithms were implemented applying low-power design techniques, dynamic voltage scaling, and application-aware dynamic power management. The algorithmic contribution lies in the MVC energy reduction by shorten the computational complexity of the energy-hungriest encoder blocks, the Mode Decision and the Motion and Disparity Estimation. The proposed energy-efficient algorithms take advantage of the video properties along with the strong correlation available within the 3D-Neighborhood (spatial, temporal and disparity) space in order to efficiently reduce energy consumption. Our Multi-Level Fast Mode Decision defines two complexity reduction operation modes able to provide, on average, 63% and 71% of complexity reduction, respectively. Additionally, the proposed Fast ME/DE algorithm reduces the complexity in about 83%, for the average case. Considering the run-time variations posed by changing coding parameters and video content, an Energy-Aware Complexity Adaptation algorithm is proposed to handle the energy versus coding efficiency tradeoff while providing graceful quality degradation under severe battery draining scenarios by employing asymmetric video coding. Finally, to cope with eventual video quality losses posed by the energy-efficient algorithms, we define a video quality management technique based on our Hierarchical Rate Control. The Hierarchical Rate Control implements a frame-level rate control based on a Model Predictive Controller able to increase in 0.8dB (Bjøntegaard) the overall video quality. The video quality is increased in 1.9dB (Bjøntegaard) with the integration of the basic unit-level rate control designed using Markov Decision Process and Reinforcement Learning. Even though the energy-efficient algorithms drive to meaningful energy reduction, hardware acceleration is mandatory to reach the energy-efficiency demanded by the MVC. Aware of this requirement, this thesis brings architectural solutions for the Motion and Disparity Estimation unit focusing on energy reduction while attending real-time throughput requirements. To achieve the desired results, as shown along this volume, there is a need to reduce the energy related to the ME/DE computation and related to the intense memory communication. Therefore, the ME/DE architectures incorporate the Fast ME/DE algorithm in order to reduce the computational complexity while the memory hierarchy was carefully designed to find the optimal energy tradeoff between external memory accesses and on-chip video memory size. Statistical analysis where used to define the size and organization of the on-chip cache memory while avoiding increased memory misses and the consequent data retransmission. A prefetching technique based on search window prediction also supports the reduction of external memory access. Moreover, a memory power gating technique based on dynamic search window formation and an application aware power management were proposed to reduce the static energy consumption related to on-chip video memory. To implement these techniques a SRAM memory featuring multiple power states was used. The architectural contribution contained in this thesis extends the state-of-the-art by achieving real-time ME/DE processing for 4-views HD1080p running at 300MHz and consuming 57mW.

Este trabalho trata da aplicação de técnicas de minimização de consumo de potência para blocos digitais para o algoritmo de SAD e o decodificador H.264/AVC Intra-Only. Na descrição de hardware são acrescidas as técnicas de paralelismo e pipeline. Na síntese física e lógica, incluem-se as técnicas de inativação do relógio ( clock gating), múltiplas tensões de threshold, diferentes tecnologias e diferentes tensões de alimentação. A síntese é feita nas ferramentas da CadenceTM com exploração arquitetural e apresenta uma menor energia por operação, quando exigido desempenho equivalente (isoperformance ) para SAD, em baixa frequência, alto paralelismo e, principalmente, com um estágio de pipeline. Além disso, tecnologias CMOS mais avançadas diminuem o consumo de potência dinâmica e, em alguns casos, também diminuem a potência estática por gate equivalente, se utilizadas células High-VT e tensão de alimentação a menor possível. Outro fator a ser destacado é o uso do clock gating que no caso das arquiteturas de SAD, em vez de diminuir, aumenta o consumo de potência dinâmica. Neste trabalho foi realizada a síntese do decodificador Intra-Only. O decodificador com clock gating apresenta um menor consumo de potência, mostrando um caso em que esta técnica é benéfica. Além disso, a utilização de uma tecnologia CMOS 65 nm e, consequentemente, tensão de alimentação menor, levou a uma sensível diminuição no consumo de potência em relação a outros trabalhos similares. / This work presents low-power techniques applications to digital blocks in the SAD algorithm and in the Intra-Only H.264/AVC decoder. In the hardware description, we add parallelism and pipeline techniques. In the logical and physical synthesis exploration, includes the clock gating, multiple threshold voltage, different technologies and multiple supply voltage. The synthesis are done in the CadenceTM tools and show a smaller energy per operation in isoperformance for SAD at low frequency, high parallelism and, mainly, with one pipeline stage. In addition to that, more advanced CMOS technologies decrease the dynamic power consumption and, also, decrease the static power for equivalent gates, if using High-VT cells and lowest possible power supply. Another factor is the clock gating use that in the SAD architecture, instead of decreasing, increases the dynamic power consumption. In this work the design of an Intra-Only H.264/AVC Decoder was performed. This design with clock gating presents lower power consumption, showing a case in which this technique is beneficial in terms of dynamic power. Besides that, the 65 nm CMOS technology uses a lower power supply, resulting in lower power consumption in comparison to other related works.

A compressão de vídeo é essencial para aplicações que manipulam vídeos digitais, em função da enorme quantidade de informação necessária para representar um vídeo sem nenhum tipo de compressão. Esta tese apresenta o desenvolvimento de soluções arquiteturais dedicadas e de alto desempenho para a compressão de vídeos, com foco no padrão H.264/AVC. O padrão H.264/AVC é o mais novo padrão de compressão de vídeo da ITU-T e da ISO e atinge as mais elevadas taxas de compressão dentre todos os padrões de codificação de vídeo existentes. Este padrão também possui a maior complexidade computacional dentre os padrões atuais. Esta tese apresenta soluções arquiteturais para os módulos da estimação de movimento, da compensação de movimento, das transformadas diretas e inversas e da quantização direta e inversa. Inicialmente, são apresentados alguns conceitos básicos de compressão de vídeo e uma introdução ao padrão H.264/AVC, para embasar as explicações das soluções arquiteturais desenvolvidas. Então, as arquiteturas desenvolvidas para os módulos das transformadas diretas e inversas, da quantização direta e inversa, da estimação de movimento e da compensação de movimento são apresentadas. Todas as arquiteturas desenvolvidas foram descritas em VHDL e foram mapeadas para FPGAs Virtex-II Pro da Xilinx. Alguns dos módulos foram, também, sintetizados para standard-cells. Os resultados obtidos através da síntese destas arquiteturas são apresentados e discutidos. Para todos os casos, os resultados de síntese indicaram que as arquiteturas desenvolvidas estão aptas para atender as demandas de codecs H.264/AVC direcionados para vídeos de alta resolução. / Video coding is essential for applications based in digital videos, given the enormous amount of bits which are required to represent a video sequence without compression. This thesis presents the design of dedicated and high performance architectures for video compression, focusing in the H.264/AVC standard. The H.264/AVC standard is the latest ITU-T and ISO standard for video compression and it reaches the highest compression rates amongst all the current video coding standards. This standard has also the highest computational complexity among all of them. This thesis presents architectural solutions for the modules of motion estimation, motion compensation, forward and inverse transforms and forward and inverse quantization. Some concepts of video compression and an introduction to the H.264/AVC standard are presented and they serve as basis for the architectural developments. Then, the designed architectures for forward and inverse transforms, forward and inverse quantization, motion estimation and motion compensation are presented. All designed architectures were described in VHDL and they were mapped to Xilinx Virtex-II Pro FPGAs. Some modules were also synthesized into standard-cells. The synthesis results are presented and discussed. For all cases, the synthesis results indicated that the architectures developed in this work are able to meet the demands of H.264/AVC codecs targeting high resolution videos.

Esta dissertação é composta de duas partes principais em que apresenta, em sua primeira parte, o desenvolvimento de uma arquitetura de hardware para compensação de movimento para decodificadores de vídeo segundo o padrão H.264/AVC. A segunda parte apresenta a modelagem de uma arquitetura de hardware para codificação de vídeo segundo o mesmo padrão. Também são apresentados os conceitos básicos da codificação e decodificação de vídeo digital segundo o padrão H.264/AVC. A arquitetura desenvolvida para compensação de movimento, denominada HP422- MoCHA (High Profile 4:2:2 Motion Compensation Hardware Architecture) (ZATT, 2008), baseada na arquitetura MoCHA (Motion Compensator Hardware Architecture) (AZEVEDO, 2007), suporta o conjunto de ferramentas da compensação de movimento para o perfil High 4:2:2 do H.264/AVC. Esta arquitetura está particionada em três blocos principais: Preditor de Vetores de Movimento, Acesso à Memória e Processador de Amostras. Esses blocos funcionam na forma de um pipeline, existindo buffers entre os mesmos para armazenar os resultados intermediários. A descrição foi desenvolvida com a linguagem VHDL e alcança desempenho para decodificar, em tempo real, vídeos HDTV 1920x1080 a 30 quadros por segundo. Na literatura atual não foi encontrada nenhuma solução detalhada para a compensação de movimento no perfil High 4:2:2 do padrão H.264/AVC. Uma nova estrutura para interpolação de amostra na compensação de movimento foi proposta, sendo que sua versão para o Perfil Main se mostra 17% mais compacta, em termos de gates, que a solução mais compacta encontrada na literatura, sem degradação de performance. A segunda parte do texto detalha a modelagem de uma arquitetura de codificação de vídeo segundo o H.264/AVC. A descrição utiliza a linguagem SystemC e consumiu aproximadamente 15.000 linhas de código. Seu projeto foi desenvolvido com o objetivo de codificar vídeo H.264/AVC segundo o perfil Main do padrão com desempenho para codificar vídeos 1920x1080 em tempo real, a 30 quadros por segundo. A modelagem alcançou o objetivo principal de chegar a uma implementação funcional de um codificador, embora assumindo diversas restrições de codificação, permitindo a caracterização temporal e de comunicação do codificador. Dessa forma, o modelo se mostra uma poderosa ferramenta para o desenvolvimento do sistema de codificação em HW, desde a etapa de projeto até a verificação final. Não foi encontrado na literatura, até o presente momento, nenhum trabalho que descreva uma modelagem em alto nível de um hardware para o codificador, ou mesmo para o decodificador, de vídeo H.264/AVC. / This thesis is comprised by two main parts that present, in the first part, the development of a motion compensation hardware architecture for video decoders in compliance with the H.264/AVC standard. The second part presents a hardware architecture modeling for a video encoder compliant to the same video standard. The digital video coding basics in the H.264/AVC standard are also reviewed. The developed motion compensation hardware architecture, named HP422-MoCHA (High Profile 4:2:2 Motion Compensation Hardware Architecture) (ZATT, 2008), is based on the MoCHA (Motion Compensator Hardware Architecture) (AZEVEDO, 2007) architecture. It supports the motion compensation toolset for the H.264/AVC High 4:2:2 profile. This architecture is divided in three main modules: Motion Vector Predictor, Memory Access and Sample Processor. These modules work in a pipeline and are interfaced by buffers to store the intermediate data. The architecture was described in the VHDL language and reaches the required throughput for real time decoding of HDTV 1920x1080 video sequences at 30 frames per second. In the current literature another detailed motion compensation solution for the H.264/AVC High 4:2:2 could not be found. A new filtering organization for the motion compensation sample interpolator was proposed and its Main profile version reduces 17% the gate count in comparison to the smallest solution found in the literature, without any performance degradation. The second part of the thesis details the modeling of a hardware architecture for a video encoder for the H.264/AVC standard. The model was described in SystemC language and used 15,000 source code lines. The project was designed for real time encoding of Main profile H.264/AVC for 1920x1080 video sequences at 30 frames per second. The model supported the main objective which was to obtain a functional encoder implementation, despite of the several encoding restrictions, permitting the temporal and communications characterization of the encoder. The model is presented as a powerful tool for the hardware video encoder development, as it is useful from the initial design to the final verification. No other hardware encoder or decoder modeling description was found in the current literature for the H.264/AVC video coding standard.

Apesar de as capacidades de transmissão e de armazenamento dos dispositivos continuarem crescendo, a compressão ainda é essencial em aplicações que trabalham com vídeo. Com a compressão reduz-se significativamente a quantidade de bits necessários para se representar uma seqüência de vídeo. Dentre os padrões de compressão de vídeo digital, o mais novo é o H.264/AVC. Este padrão alcança as mais elevadas taxas de compressão se comparado com os padrões anteriores mas, por outro lado, possui uma elevada complexidade computacional. A complexidade computacional elevada dificulta o desenvolvimento em software de aplicações voltadas a definições elevadas de imagem, considerando a tecnologia atual. Assim, tornam-se indispensáveis implementações em hardware. Neste escopo, este trabalho aborda o desenvolvimento de uma arquitetura para estimação de movimento de blocos de tamanhos variáveis segundo o padrão H.264/AVC de compressão de vídeo digital. Esta arquitetura utiliza o algoritmo full search e SAD como critério de similaridade. Além disso, a arquitetura é capaz de gerar os 41 diferentes vetores de movimento referentes a um macrobloco e definidos pelo padrão. A solução arquitetural proposta neste trabalho foi descrita em VHDL e mapeada para FPGAs da Xilinx. Também foi desenvolvida uma versão standard cell da arquitetura. Considerando-se as versões da arquitetura com síntese direcionada para FPGA, os resultados mostraram que a arquitetura pode ser utilizada em aplicações voltadas para alta definição como SDTV ou HDTV. Para a versão standard cells da arquitetura os resultados indicam que ela pode ser utilizada para aplicações SDTV. / The transmission and storage capabilities of the digital communications and processing continue to grow. However, compression is still necessary in video applications. With compression, the amount of bits necessary to represent a video sequence is dramatically reduced. Amongst the video compression standards, the latest one is the H.264/AVC. This standard reaches the highest compression rates when compared to the previous standards. On the other hand, it has a high computational complexity. This high computational complexity makes it difficult the development of applications targeting high definitions when a software implementation running in a current technology is considered. Thus, hardware implementations become essential. Addressing the hardware architectures, this work presents the architectural design for the variable block-size motion estimation defined in the H.264/AVC standard. This architecture is based on full search motion estimation algorithm and SAD calculation. This architecture is able to produce the 41 motion vectors within a macroblock that are specified in the standard. The architecture designed in this work was described in VHDL and it was mapped to Xilinx FPGAs. Extensive simulations of the hardware architecture and comparisons to the software implementation of the same variable-size algorithm were used to validate the architecture. It was also synthesized to standard cells. Considering the synthesis results, the architecture reaches real time for high resolution videos, as HDTV when mapped to FPGAs. The standard cells version of this architecture is able to reach real time for SDTV resolution, considering a physical synthesis to 0.18µm CMOS.

A compressão de vídeo é essencial para aplicações que manipulam vídeos digitais, em função da enorme quantidade de informação necessária para representar um vídeo sem nenhum tipo de compressão. Esta tese apresenta o desenvolvimento de soluções arquiteturais dedicadas e de alto desempenho para a compressão de vídeos, com foco no padrão H.264/AVC. O padrão H.264/AVC é o mais novo padrão de compressão de vídeo da ITU-T e da ISO e atinge as mais elevadas taxas de compressão dentre todos os padrões de codificação de vídeo existentes. Este padrão também possui a maior complexidade computacional dentre os padrões atuais. Esta tese apresenta soluções arquiteturais para os módulos da estimação de movimento, da compensação de movimento, das transformadas diretas e inversas e da quantização direta e inversa. Inicialmente, são apresentados alguns conceitos básicos de compressão de vídeo e uma introdução ao padrão H.264/AVC, para embasar as explicações das soluções arquiteturais desenvolvidas. Então, as arquiteturas desenvolvidas para os módulos das transformadas diretas e inversas, da quantização direta e inversa, da estimação de movimento e da compensação de movimento são apresentadas. Todas as arquiteturas desenvolvidas foram descritas em VHDL e foram mapeadas para FPGAs Virtex-II Pro da Xilinx. Alguns dos módulos foram, também, sintetizados para standard-cells. Os resultados obtidos através da síntese destas arquiteturas são apresentados e discutidos. Para todos os casos, os resultados de síntese indicaram que as arquiteturas desenvolvidas estão aptas para atender as demandas de codecs H.264/AVC direcionados para vídeos de alta resolução. / Video coding is essential for applications based in digital videos, given the enormous amount of bits which are required to represent a video sequence without compression. This thesis presents the design of dedicated and high performance architectures for video compression, focusing in the H.264/AVC standard. The H.264/AVC standard is the latest ITU-T and ISO standard for video compression and it reaches the highest compression rates amongst all the current video coding standards. This standard has also the highest computational complexity among all of them. This thesis presents architectural solutions for the modules of motion estimation, motion compensation, forward and inverse transforms and forward and inverse quantization. Some concepts of video compression and an introduction to the H.264/AVC standard are presented and they serve as basis for the architectural developments. Then, the designed architectures for forward and inverse transforms, forward and inverse quantization, motion estimation and motion compensation are presented. All designed architectures were described in VHDL and they were mapped to Xilinx Virtex-II Pro FPGAs. Some modules were also synthesized into standard-cells. The synthesis results are presented and discussed. For all cases, the synthesis results indicated that the architectures developed in this work are able to meet the demands of H.264/AVC codecs targeting high resolution videos.

Esta dissertação é composta de duas partes principais em que apresenta, em sua primeira parte, o desenvolvimento de uma arquitetura de hardware para compensação de movimento para decodificadores de vídeo segundo o padrão H.264/AVC. A segunda parte apresenta a modelagem de uma arquitetura de hardware para codificação de vídeo segundo o mesmo padrão. Também são apresentados os conceitos básicos da codificação e decodificação de vídeo digital segundo o padrão H.264/AVC. A arquitetura desenvolvida para compensação de movimento, denominada HP422- MoCHA (High Profile 4:2:2 Motion Compensation Hardware Architecture) (ZATT, 2008), baseada na arquitetura MoCHA (Motion Compensator Hardware Architecture) (AZEVEDO, 2007), suporta o conjunto de ferramentas da compensação de movimento para o perfil High 4:2:2 do H.264/AVC. Esta arquitetura está particionada em três blocos principais: Preditor de Vetores de Movimento, Acesso à Memória e Processador de Amostras. Esses blocos funcionam na forma de um pipeline, existindo buffers entre os mesmos para armazenar os resultados intermediários. A descrição foi desenvolvida com a linguagem VHDL e alcança desempenho para decodificar, em tempo real, vídeos HDTV 1920x1080 a 30 quadros por segundo. Na literatura atual não foi encontrada nenhuma solução detalhada para a compensação de movimento no perfil High 4:2:2 do padrão H.264/AVC. Uma nova estrutura para interpolação de amostra na compensação de movimento foi proposta, sendo que sua versão para o Perfil Main se mostra 17% mais compacta, em termos de gates, que a solução mais compacta encontrada na literatura, sem degradação de performance. A segunda parte do texto detalha a modelagem de uma arquitetura de codificação de vídeo segundo o H.264/AVC. A descrição utiliza a linguagem SystemC e consumiu aproximadamente 15.000 linhas de código. Seu projeto foi desenvolvido com o objetivo de codificar vídeo H.264/AVC segundo o perfil Main do padrão com desempenho para codificar vídeos 1920x1080 em tempo real, a 30 quadros por segundo. A modelagem alcançou o objetivo principal de chegar a uma implementação funcional de um codificador, embora assumindo diversas restrições de codificação, permitindo a caracterização temporal e de comunicação do codificador. Dessa forma, o modelo se mostra uma poderosa ferramenta para o desenvolvimento do sistema de codificação em HW, desde a etapa de projeto até a verificação final. Não foi encontrado na literatura, até o presente momento, nenhum trabalho que descreva uma modelagem em alto nível de um hardware para o codificador, ou mesmo para o decodificador, de vídeo H.264/AVC. / This thesis is comprised by two main parts that present, in the first part, the development of a motion compensation hardware architecture for video decoders in compliance with the H.264/AVC standard. The second part presents a hardware architecture modeling for a video encoder compliant to the same video standard. The digital video coding basics in the H.264/AVC standard are also reviewed. The developed motion compensation hardware architecture, named HP422-MoCHA (High Profile 4:2:2 Motion Compensation Hardware Architecture) (ZATT, 2008), is based on the MoCHA (Motion Compensator Hardware Architecture) (AZEVEDO, 2007) architecture. It supports the motion compensation toolset for the H.264/AVC High 4:2:2 profile. This architecture is divided in three main modules: Motion Vector Predictor, Memory Access and Sample Processor. These modules work in a pipeline and are interfaced by buffers to store the intermediate data. The architecture was described in the VHDL language and reaches the required throughput for real time decoding of HDTV 1920x1080 video sequences at 30 frames per second. In the current literature another detailed motion compensation solution for the H.264/AVC High 4:2:2 could not be found. A new filtering organization for the motion compensation sample interpolator was proposed and its Main profile version reduces 17% the gate count in comparison to the smallest solution found in the literature, without any performance degradation. The second part of the thesis details the modeling of a hardware architecture for a video encoder for the H.264/AVC standard. The model was described in SystemC language and used 15,000 source code lines. The project was designed for real time encoding of Main profile H.264/AVC for 1920x1080 video sequences at 30 frames per second. The model supported the main objective which was to obtain a functional encoder implementation, despite of the several encoding restrictions, permitting the temporal and communications characterization of the encoder. The model is presented as a powerful tool for the hardware video encoder development, as it is useful from the initial design to the final verification. No other hardware encoder or decoder modeling description was found in the current literature for the H.264/AVC video coding standard.

Apesar de as capacidades de transmissão e de armazenamento dos dispositivos continuarem crescendo, a compressão ainda é essencial em aplicações que trabalham com vídeo. Com a compressão reduz-se significativamente a quantidade de bits necessários para se representar uma seqüência de vídeo. Dentre os padrões de compressão de vídeo digital, o mais novo é o H.264/AVC. Este padrão alcança as mais elevadas taxas de compressão se comparado com os padrões anteriores mas, por outro lado, possui uma elevada complexidade computacional. A complexidade computacional elevada dificulta o desenvolvimento em software de aplicações voltadas a definições elevadas de imagem, considerando a tecnologia atual. Assim, tornam-se indispensáveis implementações em hardware. Neste escopo, este trabalho aborda o desenvolvimento de uma arquitetura para estimação de movimento de blocos de tamanhos variáveis segundo o padrão H.264/AVC de compressão de vídeo digital. Esta arquitetura utiliza o algoritmo full search e SAD como critério de similaridade. Além disso, a arquitetura é capaz de gerar os 41 diferentes vetores de movimento referentes a um macrobloco e definidos pelo padrão. A solução arquitetural proposta neste trabalho foi descrita em VHDL e mapeada para FPGAs da Xilinx. Também foi desenvolvida uma versão standard cell da arquitetura. Considerando-se as versões da arquitetura com síntese direcionada para FPGA, os resultados mostraram que a arquitetura pode ser utilizada em aplicações voltadas para alta definição como SDTV ou HDTV. Para a versão standard cells da arquitetura os resultados indicam que ela pode ser utilizada para aplicações SDTV. / The transmission and storage capabilities of the digital communications and processing continue to grow. However, compression is still necessary in video applications. With compression, the amount of bits necessary to represent a video sequence is dramatically reduced. Amongst the video compression standards, the latest one is the H.264/AVC. This standard reaches the highest compression rates when compared to the previous standards. On the other hand, it has a high computational complexity. This high computational complexity makes it difficult the development of applications targeting high definitions when a software implementation running in a current technology is considered. Thus, hardware implementations become essential. Addressing the hardware architectures, this work presents the architectural design for the variable block-size motion estimation defined in the H.264/AVC standard. This architecture is based on full search motion estimation algorithm and SAD calculation. This architecture is able to produce the 41 motion vectors within a macroblock that are specified in the standard. The architecture designed in this work was described in VHDL and it was mapped to Xilinx FPGAs. Extensive simulations of the hardware architecture and comparisons to the software implementation of the same variable-size algorithm were used to validate the architecture. It was also synthesized to standard cells. Considering the synthesis results, the architecture reaches real time for high resolution videos, as HDTV when mapped to FPGAs. The standard cells version of this architecture is able to reach real time for SDTV resolution, considering a physical synthesis to 0.18µm CMOS.