This thesis introduces the use of technological failure in visual arts, described as glitch art in the Anglo-American literature, and reveals its specific qualities. The author examines creative exploration of glitch both in image compression formats, and in the user interface of web sites, computer games or operating systems. In addition, the research presents arguments that advocate glitch art in a broader artistic discourse. It does so firstly by analogy, when it compares glitch art manifestations to conceptual and visual qualities of the paradigmatic works of art and artistic movements, and secondly by Dickie's institutional classification, when it analyzes glitch art communities and appreciation by the curatorial, critical and academic public. The central argument of this thesis is that glitch art next to a purely aesthetic experience provides an insight into the heart of technology, which exposes its functionality. Thus it contributes to a deeper understanding of its physical, structural and ideological fundamentals, that have become in everyday life almost invisible due to the logic of immediacy. Given the highly relative nature of the term glitch the thesis does not seek a hard definition of its specifics, but rather asks the cause of this naming (designation) that is why we perceive a...

This thesis is a qualitative research and design project based on the concept of glitch. Glitch, typically associated with technical malfunctions, is examined here from a philosophical perspective with emphasis on the phenomenological aspect. A glitch in this thesis is seen as beyond an error; instead it is a moment of disruption, a subjective experience that prompt re-examination of our perception. By exploring the notion of glitch, the aim is to discover glitch given form and to challenge conventional design practices. The creative process involved theoretical exploration, qualitative interviews, and model making. Through research and interviews, a series of glitch volumes (X, Y, Z, W) were created based on personal glitch experiences.

This thesis presents two contributions to the FPGA CAD domain. First, a study of glitch power in a commercial FPGA is presented, showing that glitch power in FPGAs is significant. A CAD algorithm is presented that reduces glitch power at the post-routing stage by taking advantage of don't-cares in the logic functions of the circuit. This method comes at no cost to area or performance. The second contribution of this thesis is a study of FPGA CAD algorithm noise {random choices which can have an unpredictable effect on the circuit as a whole. An analysis of noise in the logic synthesis, technology mapping, and placement stages is presented. A series of early performance and power metrics is proposed, in an effort to find the best circuit implementation in the noise space.

This thesis presents two contributions to the FPGA CAD domain. First, a study of glitch power in a commercial FPGA is presented, showing that glitch power in FPGAs is significant. A CAD algorithm is presented that reduces glitch power at the post-routing stage by taking advantage of don't-cares in the logic functions of the circuit. This method comes at no cost to area or performance. The second contribution of this thesis is a study of FPGA CAD algorithm noise {random choices which can have an unpredictable effect on the circuit as a whole. An analysis of noise in the logic synthesis, technology mapping, and placement stages is presented. A series of early performance and power metrics is proposed, in an effort to find the best circuit implementation in the noise space.

The past is a statement; the future a question. Henri Cartier-Bresson provides us with an interpretation of the “now” with the decisive moment and it is through this lens that I examine the glitch. Like the street photography style that Cartier-Bresson pioneered, the glitch artist role is not to simply create, but lies in inviting and reacting to conditions that will permit art to happen. Similar to the camera’s shutter being triggered, the glitch is initialized in a moment of uncertainty by our analog selves and is revealed to be dissident code that is set free from the pristine constructs of the digital format. As the glitch is an affective event that happens in real time, or in a moment, it can be recorded, captured and documented as a breakthrough of noise separated from the signal. As a culture, we tend to filter out and defend against the noise of the glitch while keeping the myth of perfect signal alive. I would suggest that we welcome the noise as a type of natural wilderness in the machine that reveals the illusion of the digital era and blurs the lines between transcription and transcoding.

No description available.

No description available.

The miscommunication between sender and receiver during transcoding indexes specific historical moments similarly to analog film's indexical trace. Iconography and glitch art begin to establish glitch's deictic index. The glitch aesthetic exposes societal paranoia by illustrating dependence on the digital and fear of system failure. With the advent of video sharing sites like Youtube and popular cyberfilms, the glitch aesthetic has evolved into a pop culture artifact.

In modern cryptanalysis, an active attacker may induce errors during the computation of a cryptographic algorithm and exploit the faulty results to extract information about the secret key in embedded systems. This kind of attack is called a fault attack. There have been various attack mechanisms with diff erent fault models proposed in the literature. Among them, clock glitch faults support practically dangerous fault attacks on cryptosystems. This thesis presents an FPGA-based practical testbed for characterizing exploitable clock glitch faults and uniformly evaluating cryptographic systems against them. Concentrating on Advanced Encryption Standard (AES), simulation and experimental results illustrates proper features for the clock glitches generated by the implemented on-chip glitch generator. These glitches can be injected reliably with acceptably accurate timing. The produced faults are random but their eff ect domain is finely controllable by the attacker. These features makes clock glitch faults practically suitable for future possible complete fault attacks on AES. This research is important for investigating the viability and analysis of fault injections on various cryptographic functions in future embedded systems.

In modern cryptanalysis, an active attacker may induce errors during the computation of a cryptographic algorithm and exploit the faulty results to extract information about the secret key in embedded systems. This kind of attack is called a fault attack. There have been various attack mechanisms with diff erent fault models proposed in the literature. Among them, clock glitch faults support practically dangerous fault attacks on cryptosystems. This thesis presents an FPGA-based practical testbed for characterizing exploitable clock glitch faults and uniformly evaluating cryptographic systems against them. Concentrating on Advanced Encryption Standard (AES), simulation and experimental results illustrates proper features for the clock glitches generated by the implemented on-chip glitch generator. These glitches can be injected reliably with acceptably accurate timing. The produced faults are random but their eff ect domain is finely controllable by the attacker. These features makes clock glitch faults practically suitable for future possible complete fault attacks on AES. This research is important for investigating the viability and analysis of fault injections on various cryptographic functions in future embedded systems.