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This dissertation describes the development of a process for the precise positioning of semiconductor nanoparticles grown by hot wire chemical vapor deposition and thermal chemical vapor deposition on amorphous dielectrics, and it presents two studies that demonstrate the process. The studies entailed growth and characterization using surface science techniques and scanning electron microscopy. The two systems, Ge nanoparticles on HfO₂ and Si nanoparticles on Si₃N₄, are of interest because their electronic properties show potential in flash memory devices. The positioning technique resulted in nanoparticles deposited within 20 nm diameter feature arrays having a 6x10¹⁰ cm⁻² feature density. Self-assembling diblock copolymer poly(styrene-b-methyl methacrylate) thin films served as the patterning soft mask. The diblock copolymer features were transferred using a CHF₃/O₂ reactive ion etch chemistry into a thin film SiO₂ hard mask to expose the desired HfO₂ or Si₃N₄ deposition surface underneath. Selective deposition upon exposed pore bottoms was performed at conditions where adatom accumulation occurred on the HfO₂ or Si₃N₄ surfaces and not upon the SiO₂ mask template. The selective deposition temperatures for the Ge/HfO₂ and Si/Si₃N₄ systems were 700 to 800 K and 900 to 1025 K, respectively. Germanium nucleation on HfO₂ is limited from hot wire chemical vapor deposition by depositing nanoparticles within 67% of the available features. Unity filling of features with Ge nanoparticles was achieved using room temperature adatom seeding before deposition. Nanoparticle shape and size are regulated through the Ge interactions with the SiO₂ feature sidewalls with the adatom removal rate from the features being a function of temperature. The SiO₂ mask limited Ge nanoparticle growth laterally to within ~5 nm of the hard mask at 800 K. Silicon deposition on patterned Si₃N₄ has multiple nanoparticles, up to four, within individual 20 nm features resulting from the highly reactive Si₃N₄ deposition surface. Silicon nucleation and continued nanoparticle growth is a linear function of deposition flux and an inverse function of sample temperature. Diblock copolymer organization can be directed into continuous crystalline domains having ordered minority phases in a process known as graphoepitaxy. In graphoepitaxy forced alignment within microscopic features occurs provided certain dimensional constraints are satisfied. Graphoepitaxy was attempted to precisely locate 20 nm diameter features for selective Ge or Si deposition and initial studies are presented. In addition to precise nanoparticle positioning studies, kinetic studies were performed using the Ge/HfO₂ material system. Germanium hot wire chemical vapor deposition on unpatterned HfO₂ surfaces was interpreted within the mathematical framework of mean-field nucleation theory. A critical cluster size of zero and critical cluster activation energy of 0.4 to 0.6 eV were estimated. Restricting HfO₂ deposition area to a 200 nm to 100 [mu]m feature-width range using SiO₂ decreases nanoparticle density compared to unpatterned surfaces. The studies reveal the activation energies for surface diffusion, nucleation, and Ge etching of SiO₂ are similar in magnitude. Comparable activation energies for Ge desorption, surface diffusion and cluster formation obscure the change with temperature an individual process rate has on nanoparticle growth characteristics as the feature size changes. / text

The continuous improvement in the semiconductor industry has been successfully achieved by the reducing dimensions of CMOS (complementary metal oxide semiconductor) technology. For the last four decades, the scaling down of physical thickness of SiO₂ gate dielectrics has improved the speed of output drive current by shrinking of transistor area in front-end-process of integrated circuits. A higher number of transistors on chip resulting in faster speed and lower cost can be allowable by the scaling down and these fruitful achievements have been mainly made by the thinning thickness of one key component - Gate Dielectric - at Si based MOSFET (metal-oxide-semiconductor field effect transistor) devices. So far, SiO₂ (silicon dioxide) gate dielectric having the excellent material and electrical properties such as good interface (i.e., Dit ~ 2x10¹⁰ eV⁻¹cm⁻²), low gate leakage current, higher dielectric breakdown immunity (≥10MV/cm) and excellent thermal stability at typical Si processing temperature has been popularly used as the leading gate oxide material. The next generation Si based MOSFETs will require more aggressive gate oxide scaling to meet the required specifications. Since high-k dielectrics provide the same capacitance with a thicker film, the leakage current reduction, therefore, less the standby power consumption is one of the huge advantages. Also, it is easier to fabricate during the process because the control of film thickness is still not in the critical range compared to the same leakage current characteristic of SiO₂ film. HfO₂ based gate dielectric is considered as the most promising candidate among materials being studied since it shows good characteristics with conventional Si technology and good device performance has been reported. However, it has still many problems like insufficient thermals stability on silicon such as low crystallization temperature, low k interfacial regrowth, charge trapping and so on. The integration of hafnium based high-k dielectric into CMOS technology is also limited by major issues such as degraded channel mobility and charge trapping. One approach to overcome these obstacles is using alternative substrate materials such as SiGe, GaAs, InGaAs, and InP to improve channel mobility. / text

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Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

Thesis (Ph. D.)--University of Texas at Austin, 2004. / Supervisor: Jack C. Lee. Vita. Includes bibliographical references. Also available from UMI.

Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (M.S.)--Rochester Institute of Technology, 2006. / Typescript. Includes bibliographical references (leaves 145-146).