The study of coding theory aims to detect and correct the errors during the transmission of the data. It enhances the quality of data transmission and provides better control over the noisy channels.The perfect codes are collected and analyzed in the premises of the Hamming metric.This classification yields that there exists only a few perfect codes. The perfect codes do not guarantee the perfection by all means but just satisfy certain bound and properties. The detection and correction of errors is always very important for better data transmission.

A modified, single error-correcting, and double error detecting Hamming code, hereafter referred to as modified SEC-DED Hamming code, is proposed in this research. The code requires fewer logic gates to implement than the SEC-DED Hamming code. Also, unlike the popular Hsiao's code, the proposed code can determine the error in the received word from its syndrome location in the parity check matrix. A detailed analysis of the area and power utilization by the encoder and decoder circuits of the modified SEC-DED Hamming code is also discussed. Results demonstrate that this code is an excellent alternative to Hsiao's code as the area and power values are very similar. In addition, the ability to locate the error in the received word from its syndrome is also of particular interest. Primitive polynomials play a crucial role in the hardware realizations for error-correcting codes. This research describes an implementation of a scalable primitive polynomial circuit with coefficients in GF(2). The standard cell area and power values for various degrees of the circuit are analyzed. The physical design of a degree 6 primitive polynomial computation circuit is also provided. In addition to the codes, a background of the already existing SPX GCD computation algorithm is provided. Its implementation revealed that the combinational implementation of the SPX algorithm utilizes a significantly lesser area than Euclid's algorithm. The FSMD implementation of the SPX algorithm reduces both dynamic and leakage power consumption. The physical design of the GCD computation using the SPX algorithm is also provided.

In this thesis, bit-by-bit power allocation in order to minimize mean-squared error (MSE) distortion of a basic communication system is studied. This communication system consists of a quantizer. There may or may not be a channel encoder and a Binary Phase Shift Keying (BPSK) modulator. In the quantizer, natural binary mapping is made. First, the case where there is no channel coding is considered. In the uncoded case, hard decision decoding is done at the receiver. It is seen that errors that occur in the more significant information bits contribute more to the distortion than less significant bits. For the uncoded case, the optimum power profile for each bit is determined analytically and through computer-based optimization methods like differential evolution. For low signal-to-noise ratio (SNR), the less significant bits are allocated negligible power compared to the more significant bits. For high SNRs, it is seen that the optimum bit-by-bit power allocation gives constant MSE gain in dB over the uniform power allocation. Second, the coded case is considered. Linear block codes like (3,2), (4,3) and (5,4) single parity check codes and (7,4) Hamming codes are used and soft-decision decoding is done at the receiver. Approximate expressions for the MSE are considered in order to find a near-optimum power profile for the coded case. The optimization is done through a computer-based optimization method (differential evolution). For a simple code like (7,4) Hamming code simulations show that up to 3 dB MSE gain can be obtained by changing the power allocation on the information and parity bits. A systematic method to find the power profile for linear block codes is also introduced given the knowledge of input-output weight enumerating function of the code. The information bits have the same power, and parity bits have the same power, and the two power levels can be different.

A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.

A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.

The main subject of this thesis is creating a programme, used for channel coding demonstration. This programme will be used for teaching purposes. The programme contains various codes from simple ones, to those which almost reach Shanon’s channel capacity theorem. Specifically these are the Hamming code, cyclic code, convolutional code and LDPC code. These functions are based on theoretical background described in this thesis and have been programed in Matlab. Practical output of this thesis is user interface, where the user is able to input information word, simulate transmission through the transmission channel and observe coding and decoding for each code. This thesis also contains a comparison between individual codes, concerning bit-error rate depending on SNR and various parameters. There is a computer lab with theoretical background, assignment and sheets for convenient accomplishment of each task.

This work deals with forward error correction. In the work, basic methods and algorithms of error correction are described. For the presentation of encoding and decoding process of Hamming code, Reed-Müller code, Fire code, Reed-Solomon code and Trellis coded modulation programs in Matlab were created.

Due to the usage of complicated platforms and current high-performance space computing technology, onboard processing in small satellites is expanding. Space-cloud payload processors with Commercial Off-The-Shelf (COTS) components, that are required to be radiation-tolerant, are used to perform the onboard processing. In this thesis, the research will aim to increase the dependability of a generic space-cloud payload processor through its Solid State Drive (SSD) storage unit. To achieve this, a more dependable NAND-flash-based SSD Redundant Array of Independent Disc (RAID) storage system is designed and tested. The reliability of NAND-flash-based SSDs can suffer wear-outs due to increased Program/Erase (P/E) cycles, making them more prone to radiation effects. These radiation effects are considered non-destructive events in the form of bit errors (both single bit-flip and multiple bit-flips). Therefore, making the storage system more dependable involves increasing its reliability against non-destructive events and developing analytical models that account for the considered dynamic of the SSD RAID. The challenge that comes with achieving the aim of this thesis is twofold. First, to explore different RAID levels such that a combination of RAID levels can be incorporated into one SSD for better reliability than a RAID-1 setup. Hence, in this thesis, a RAID array of several SSDs is not considered. Furthermore, the combinations of RAID levels need to account for mixed-critical data. Second, to demonstrate, via simulation and analytical models, the impact on the reliability of the storage system. A comparison study is also undertaken due to the support that the Fourth Extended (Ext4) file system or Zettabyte File System (ZFS) may give to enhance the storage system, and since little research exists that compares the file systems in some feature categories. The solution is a RAID-5 + 6 storage system that is Error Detection And Correction (EDAC) protected by Hamming codes and Reed Solomon (RS) codes. Low-critical data is stored using RAID-5 whereas high-critical data is stored using RAID-6. The simulation of the storage system proves that low-critical stripes of data achieve single fault tolerance whereas high-critical stripes of data tolerate a maximum of 5-bit burst errors. In parallel, several Continuous Time Markov Chain (CTMC) models are analysed, which show that the proposed solution is indeed highly reliable. The comparison study is carried out in a systematic way, and the findings are established as substantial,i.e., ZFS provides greater storage system support. In summary, the results of creating the storage system and analysing it suggest that incorporating RAID-5 and RAID-6 offers better SSD RAID reliability than RAID-1. / Användningen av komplicerade plattformar och aktuell högpresterande rymdberäkningsteknik expanderar onboard-processing i små satelliter. Space-Cloud lösningar med kommersiellt tillgängliga komponenter som är toleranta mot strålningar i rymden används för att utföra onboard-processing. I detta examensarbete syftar forskningen till att förbättra tillförlitligheten hos en generisk rymd dator genom dess SSD-lagringsenhet. För att uppnå detta har ett mer tillförlitligt lagringssystem bestående av NAND-flash och RAID designats och testats. Tillförlitligheten hos NAND-flash-baserade SSD:er kan försämras då dessa kan drabbas av slitage på grund av ökade P/E cykler, vilket gör dem mer benägna för strålningseffekter. Dessa strålningseffekter anses vara icke-destruktiva i form av bit-fel (både enskilda bit-flippar och flera bit-flippar). Med denna anledning görs lagringssystemet mer tillförlitligt för att tolerera icke-destruktiva händelser. Utöver detta, utvecklas analytiska modeller som tar hänsyn till den betraktade dynamiken i SSD RAID. Utmaningen som följer med att uppnå syftet med denna avhandling är tvådelad. För det första, för att utforska olika RAID-nivåer så att en kombination av RAID-nivåer kan inkorporeras i en SSD för bättre tillförlitlighet än RAID-1. Således övervägs inte en RAID-array av flera SSD:er i denna avhandling. Dessutom måste kombinationerna av RAID-nivåer ta hänsyn till data av olika kritikalitet. För det andra, för att genom simulering och analytiska modeller indikera påverkan på lagringssystemets tillförlitlighet. En jämförelsestudie genomförs också på grund av stödet som filsystemen Ext4 eller ZFS kan ge för att förbättra lagringssystemet och eftersom det finns lite forskning som jämför filsystemen i några funktionella kategorier. Lösningen baseras på ett RAID-5+6 lagringssystem som är skyddat av Hamming-koder och RS koder för att upptäcka fel och korrigera dem. Lågkritisk data lagras med RAID-5 medan högkritisk data lagras med RAID-6. Simuleringen av lagringssystemet visar att lågkritiska datasektioner uppnår en fel tolerans mot enskilda bit-flippar medan högkritiska datasektioner kan tåla maximalt 5 bit-flippar. Samtidigt analyseras flera CTMC modeller som visar att den föreslagna lösningen verkligen är mycket tillförlitlig. Jämförelsestudien utförs på ett systematiskt sätt och resultaten fastställs som betydande, det vill säga att ZFS ger större stöd för lagringssystemet. Sammanfattningsvis antyder resultaten av att skapa lagringssystemet och analysera det att inkorporering av RAID-5 och RAID-6 erbjuder bättre tillförlitlighet för SSD RAID än RAID-1.

The thesis deals with both scheme and its implementation of water-level metering apparatus. This data are send wireless into 500 m distant station. Potential ways of solution are gradually studied and final design suggested. Detailed implementation methods are described in the following section. Ultrasonic sensors are employed for level measurement and controlling element is processor ATmega162, data are transmitted by transceiver RC1280HP. Apparatus is suggested with a view to the lowest power consumption considering it will be supplied only with a accumulator. Solving of accepting station is not a part of the thesis. Functional tested sample is understated in the execution section.

This work involves in anti-error coding systems with interleaving. At first is given summary of high-frequency use error correction codes. Below there are described two basic techniques of interleaving and their confrontation. The next text is focusing on survey and characteristics of codes which conform to submission. After selection of optimal system is verified its function in MATLAB environment. Final step is creation of functional application in C++ environment. This application serves to transmission of error correction BMP pictures.