It has been confirmed that reconfigurable computing system has potential to accelerate in large amounts of data computing. However, current trend is towards combining a microprocessor with one or many reconfigurable computing units. Thus, it might cause multiple devices to compete for System Bus that caused bus collision. And then the system performance will be limited on the bandwidth. Based on these shortcomings, this paper proposes an architecture which combines DDRx memory with a reconfigurable FPGA to construct a module with both storage and computing functions called Brain module. Brain module¡¦s instruction set is created through the extension of DDRx memory instruction. We also design the brain module controller and Hardware Management Unit. According to the definition of Software-Hardware Co-communication, the dynamically constructed Hardware Management Unit will create a hardware function call mechanism. We also establish internal data switching mechanism to achieve transmission data between memory and reconfigurable computing internal the controller. Thus, it can reduce the workload of System Bus and integrate hardware and software work. In software structure, we inherit the traditional programming language and integrate program data area and reconfigurable computing data area. Brain module data is accessed through memory mapping I/O. User can implement the software-hardware co-work by integrated programming environment,

The main objective of this research is to efficiently enable 3D die-stacked memory and heterogeneous memory systems. 3D die-stacking is an emerging technology that allows for large amounts of in-package high-bandwidth memory storage. Die-stacked memory has the potential to provide extraordinary performance and energy benefits for computing environments, from data-intensive to mobile computing. However, incorporating die-stacked memory into computing environments requires innovations across the system stack from hardware and software. This dissertation presents several architectural innovations to practically deploy die-stacked memory into a variety of computing systems. First, this dissertation proposes using die-stacked DRAM as a hardware-managed cache in a practical and efficient way. The proposed DRAM cache architecture employs two novel techniques: hit-miss speculation and self-balancing dispatch. The proposed techniques virtually eliminate the hardware overhead of maintaining a multi-megabytes SRAM structure, when scaling to gigabytes of stacked DRAM caches, and improve overall memory bandwidth utilization. Second, this dissertation proposes a DRAM cache organization that provides a high level of reliability for die-stacked DRAM caches in a cost-effective manner. The proposed DRAM cache uses error-correcting code (ECCs), strong checksums (CRCs), and dirty data duplication to detect and correct a wide range of stacked DRAM failures—from traditional bit errors to large-scale row, column, bank, and channel failures—within the constraints of commodity, non-ECC DRAM stacks. With only a modest performance degradation compared to a DRAM cache with no ECC support, the proposed organization can correct all single-bit failures, and 99.9993% of all row, column, and bank failures. Third, this dissertation proposes architectural mechanisms to use large, fast, on-chip memory structures as part of memory (PoM) seamlessly through the hardware. The proposed design achieves the performance benefit of on-chip memory caches without sacrificing a large fraction of total memory capacity to serve as a cache. To achieve this, PoM implements the ability to dynamically remap regions of memory based on their access patterns and expected performance benefits. Lastly, this dissertation explores a new usage model for die-stacked DRAM involving a hybrid of caching and virtual memory support. In the common case where system’s physical memory is not over-committed, die-stacked DRAM operates as a cache to provide performance and energy benefits to the system. However, when the workload’s active memory demands exceed the capacity of the physical memory, the proposed scheme dynamically converts the stacked DRAM cache into a fast swap device to avoid the otherwise grievous performance penalty of swapping to disk.

This doctoral thesis deals with the aspects of evaluation of balance and optimality of corporate information systems. The initiative for this specialization was given by the increasing importance that is being laid on the perception of information systems from the point of view of a business company. More and more resources are being invested in the domain of information systems, but afterwards, it is not always ascertained that the information system is such a system, one could characterize as balanced and optimal for the company today as well as in the future. Often this is because there does not exist for the company an available and easily applicable methodic how to evaluate the system. As one of the main starting points of this doctoral thesis I have chosen the methodic HOS8 that was published 5 years ago on our faculty. The newly proposed methodic HOS2009 is trying to clear up the weak points of the original HOS8 methodic that were discovered during its practical use. This is done mainly by using the information feedback from the applicants of the methodic. Within the scope of this thesis the factors influencing the level of the particular areas of the system and the influence of these areas on its general balance are being examined. With regard to the evaluation of the balance and optimality of the information system, in this thesis the problematic of determination of a balanced and optimal state of information system for a company nowadays as well in the future are being examined. As a part of the methods output the thesis presents also charts representing the general state of the system, the imbalance of the particular parts of the IS and the relationship between the areas of hardware and software. Based on the evaluation of the current state and its comparison to the balanced optimal state for the present day as well for the future, the new possible directions and strategies of further development of the IS in the company are being proposed. I see the best exploitation of the methodic HOS2009 in the company in the support of managerial decisions with impact on: the discovery of potentially problems within the scope of IS of the company, the design of a possible course of development useful for their solution, but also the usage of the methodic as a simple control mechanism.