Since its inception half a century ago, DRAM has required dynamic/active refresh operations that block read requests and decrease performance. We propose refreshing DRAM in the background without stalling read accesses to refreshing memory blocks, similar to the static/background refresh in SRAM. Our proposed Nonblocking Refresh works by refreshing a portion of the data in a memory block at a time and uses redundant data, such as Reed-Solomon codes, in the block to compute the block's refreshing/unreadable data to satisfy read requests. For proof of concept, we apply Nonblocking Refresh to server memory systems, where every memory block already contains redundant data to provide hardware failure protection. In this context, Nonblocking Refresh can utilize server memory system's existing per-block redundant data in the common-case when there are no hardware faults to correct, without requiring any dedicated redundant data of its own. Our evaluations show that on average across five server memory systems with different redundancy and failure protection strengths, Nonblocking Refresh improves performance by 16.2% and 30.3% for 16gb and 32gb DRAM chips, respectively. / Master of Science / Main memory is an essential component of computers, which stores data being actively used. The dominant type of computer main memory is Dynamic Random Access Memory (DRAM). DRAM is divided into thousands of memory cells. Each cell stores a single bit of data as a charge on a capacitor. Charges may leak over time, causing the data stored to be lost. To maintain the data stored in memory, DRAM must periodically restore charges held by memory cells through an operation known as memory refresh. Refresh operations decrease system performance because they stall read requests to refreshing memory blocks. A memory block refers to the unit of data transferred per memory request. Conventional memory systems refresh all the data within the block at a time, therefore the entire memory block is inaccessible while it is being refreshed. Our proposed Nonblocking Refresh reduces the amount of data in a memory block which is inaccessible due to refresh by refreshing only a portion the memory block at a time. To satisfy read requests, the block’s refreshing/inaccessible data is computed using redundant data. Nonblocking Refresh improves DRAM performance by refreshing DRAM in the background without stalling read accesses to refreshing memory blocks. For proof of concept, we apply Nonblocking Refresh to server memory systems, where every memory block already contains redundant data to provide hardware failure protection. In this context, Nonblocking Refresh can utilize server memory system’s existing redundant data to improve performance, without adding additional redundancy overhead. Our evaluations show that on average across five server memory systems with different redundancy and failure protection strengths, Nonblocking Refresh improves performance by 16%-30%.

In order to reduce the performance gap between the processor and the memory subsystem, many researchers attempt to integrate the processor and memory on a single chip in recent years. Therefore a new class of computer architecture: PIM (Processor-in-Memory) are investigated. For this class of architecture, we propose a new transformation and parallelizing system, SAGE, to achieve the benefits of PIM architectures by fully utilizing the capabilities of the host processor and memory processors in the PIM system. In this thesis, we focus on the weight evaluation mechanism and 1H-nM scheduling mechanism. The weight evaluation mechanism is used to evaluate the weights of P.Host and P.Mem for each task. The 1H-nM scheduling mechanism takes two different weights into account to exploit the advantages of two kinds of processors in the PIM system. The experimental results of above mechanisms are also discussed.

Future computing platforms will increasingly demand more stringent memory resiliency mechanisms due to shrinking memory cell size, reduced error margins, higher capacity, and higher reliability expectations. Traditional mechanisms, which apply error checking and correcting (ECC) codes uniformly across all memory locations, are inefficient -- Uniform protection dedicates resources to redundant information and demand higher cost for stronger protection, a fixed (worst-case based) error tolerance level, and a fixed access granularity. The design of modern computing platforms is a multi-objective optimization, balancing performance, reliability, and many other parameters within a constrained power budget. If resiliency mechanisms consume too many resources, we lose an opportunity to improve performance. Hence, it is important and necessary to enable more efficient and flexible memory resiliency mechanisms. This dissertation develops techniques that enable efficient, adaptive, and dynamically tunable memory resiliency mechanisms. First, we develop two-tiered protection, apply it to the last-level cache, and present Memory Mapped ECC (MME) and ECC FIFO. Two-tiered protection provides low-cost error detection or light-weight correction in the common case read operations, while the uncommon case error correction overhead is off-loaded to main memory namespace. MME and ECC FIFO use different schemes for managing redundant information in main memory. Both achieve 15-25% reduction in area and 9-18% reduction in power consumption of the last-level cache, while performance is degraded by only 0.7% on average. Then, we apply two-tiered protection to main memory and augment the virtual memory interface to dynamically adapt error tolerance levels according to user, system, and environmental needs. This mechanism, Virtualized ECC (V-ECC), improves system energy efficiency by 12% and degrades performance only by 1-2% for chipkill-correct level protection. V-ECC also supports ECC in a system with no dedicated storage for redundant information. Lastly, we propose the adaptive granularity memory system (AGMS) that allows different access granularities, while supporting ECC. By not wasting off-chip bandwidth for transferring unnecessary data, AGMS achieves higher throughput (by 44%) and power efficiency (by 46%) in a 4-core CMP system. Furthermore, AGMS will provide further gains in future systems, where off-chip bandwidth will be comparatively scarce. / text

Thesis (M.E.) -- University of Adelaide, Department of Electrical Engineering, 1977.

Time-shared, virtual memory systems are very complex and changes in their performance may be caused by many factors - by variations in the workload as well as changes in system configuration. The evaluation of these systems can thus best be carried out by linking results obtained from a planned programme of measurements, taken on the system, to some model of it. Such a programme of measurements is best carried out under conditions in which all the parameters likely to affect the system's performance are reproducible, and under the control of the experimenter. In order that this be possible the workload used must be simulated and presented to the target system through some form of automatic workload driver. A case study of such a methodology is presented in which the system (in this case the Edinburgh Multi-Access System) is monitored during a controlled experiment (designed and analysed using standard techniques in common use in many other branches of experimental science) and the results so obtained used to calibrate and validate a simple simulation model of the system. This model is then used in further investigation of the effect of certain system parameters upon the system performance. The factors covered by this exercise include the effect of varying: main memory size, process loading algorithm and secondary memory characteristics.

Recent graphics processing units (GPUs) have emerged as a promising platform for general purpose computing and have been shown to be very efficient in executing parallel applications with regular control and memory access behavior. Current GPU architectures primarily adopt the single-instruction multiple-thread (SIMT) programming model that balances programmability and hardware efficiency. With SIMT, the programmer writes application code to be executed by scalar threads and each thread is supported with conditional branch and fine-grained load/store instruction for ease of programming. At the same time, the hardware and software collaboratively enable the grouping of scalar threads to be executed in a vectorized single-instruction multiple-data (SIMD) in-order pipeline, simplifying hardware design. As GPUs gain momentum in being utilized in various application domains, these throughput processors will increasingly demand more efficient execution of irregular applications. Current GPUs, however, suffer from reduced thread-level parallelism, underutilization of compute resources, inefficient on-chip caching, and waste in off-chip memory bandwidth utilization for highly irregular programs with divergent control and memory accesses. In this dissertation, I develop techniques that enable simple, robust, and highly effective performance optimizations for SIMT-based throughput processor architectures such that they can better manage irregularity. I first identify that previously suggested optimizations to the divergent control flow problem suffers from the following limitations: 1) serialized execution of diverging paths, 2) lack of robustness across regular/irregular codes, and 3) limited applicability. Based on such observations, I propose and evaluate three novel mechanisms that resolve the aforementioned issues, providing significant performance improvements while minimizing implementation overhead. In the second half of the dissertation, I observe that conventional coarse-grained memory hierarchy designs do not take into account the massively multi-threaded nature of GPUs, which leads to substantial waste in off-chip memory bandwidth utilization. I design and evaluate a locality-aware memory hierarchy for throughput processors, which retains the advantages of coarse-grained accesses for spatially and temporally local programs while permitting selective fine-grained access to memory. By adaptively adjusting the access granularity, memory bandwidth and energy consumption are reduced for data with low spatial/temporal locality without wasting control overheads or prefetching potential for data with high spatial locality. / text

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Storage is a central part of computing. Driven by exponentially increasing content generation rate and a widening performance gap between memory and secondary storage, researchers are in the perennial quest to push for further innovation. This has resulted in novel ways to “squeeze” more capacity and performance out of current and emerging storage technology. Adding intelligence and leveraging new types of storage devices has opened the door to a whole new class of optimizations to save cost, improve performance, and reduce energy consumption. In this dissertation, we first develop, analyze, and evaluate three storage exten- sions. Our first extension tracks application access patterns and writes data in the way individual applications most commonly access it to benefit from the sequential throughput of disks. Our second extension uses a lower power flash device as a cache to save energy and turn off the disk during idle periods. Our third extension is designed to leverage the characteristics of both disks and solid state devices by placing data in the most appropriate device to improve performance and save power. In developing these systems, we learned that extending the storage stack is a complex process. Implementing new ideas incurs a prolonged and cumbersome de- velopment process and requires developers to have advanced knowledge of the entire system to ensure that extensions accomplish their goal without compromising data recoverability. Futhermore, storage administrators are often reluctant to deploy specific storage extensions without understanding how they interact with other ex- tensions and if the extension ultimately achieves the intended goal. We address these challenges by using a combination of approaches. First, we simplify the stor- age extension development process with system-level infrastructure that implements core functionality commonly needed for storage extension development. Second, we develop a formal theory to assist administrators deploy storage extensions while guaranteeing that the given high level goals are satisfied. There are, however, some cases for which our theory is inconclusive. For such scenarios we present an experi- mental methodology that allows administrators to pick an extension that performs best for a given workload. Our evaluation demostrates the benefits of both the infrastructure and the formal theory.

Graphics Processing Units (GPUs) are workhorses of modern performance due to their ability to achieve massive speedups on parallel applications. The massive number of threads that can be run concurrently on these systems allow applications which have data-parallel computations to achieve better performance when compared to traditional CPU systems. However, the GPU is not perfect for all types of computation. The massively parallel SIMT architecture of the GPU can still be constraining in terms of achievable performance. GPU-based systems will typically only be able to achieve between 40%-60% of their peak performance. One of the major problems affecting this effeciency is the GPU memory system, which is tailored to the needs of graphics workloads instead of general-purpose computation. This thesis intends to show the importance of memory optimizations for GPU systems. In particular, this work addresses problems of data transfer and global atomic memory contention. Using the novel AMD Fusion architecture, we gain overall performance improvements over discrete GPU systems for data-intensive applications. The fused architecture systems offer an interesting trade off by increasing data transfer rates at the cost of some raw computational power. We characterize the performance of different memory paths that are possible because of the shared memory space present on the fused architecture. In addition, we provide a theoretical model which can be used to correctly predict the comparative performance of memory movement techniques for a given data-intensive application and system. In terms of global atomic memory contention, we show improvements in scalability and performance for global synchronization primitives by avoiding contentious global atomic memory accesses. In general, this work shows the importance of understanding the memory system of the GPU architecture to achieve better application performance. / Master of Science

Beaucoup d'organisations se sont appuyées sur la créativité pour dépasser leurs concurrents et le savoir sur la façon de soutenir la créativité est devenu critique. En règle générale, la créativité aurait pour origine les individus ou un groupe de personnes travaillant ensemble. Par conséquent, dans cette thèse, notre objectif est de fournir une meilleure compréhension de la façon de faciliter la créativité à la fois au niveau individuel et de l'équipe. Pour l'équipe, nous nous concentrerons sur la créativité de l'équipe virtuelle qui a été peu étudiée malgré l’intérêt de l’analyse. Les quatre articles de cette thèse visent à fournir une meilleure compréhension de la créativité et à en identifier les déterminants tant au niveau individuel que pour l’équipe virtuelle. Nous avons analysé la littérature sur la créativité individuelle pour améliorer la compréhension de la créativité des employés. Notre analyse suggère qu'il est plus efficace de tenir compte à la fois des facteurs individuels et contextuels pour évaluer la créativité des employés. Pourtant, les interactions entre les facteurs individuels et contextuels sont multiples. Par conséquent, nous suggérons d'envisager une approche en terme de fit de la créativité entre les facteurs individuels et contextuels, ce qui nous permet également de proposer de nouvelles pratiques pour le management des ressources humaines. De plus, d’un point de vue théorique, plusieurs chercheurs suggèrent une relation étroite entre la prise de risque et la créativité des employés alors que peu d'études ont analysé cette relation. Le second article confirme qu'il existe une relation positive entre la prise de risque et la créativité des employés et aussi démontre que les facteurs individuels et contextuels issus de la littérature sur le risque et sur la créativité ont mutuellement un impact sur la prise de risque. Ensuite, sur la base de la relation étroite entre les théories du risque et de la créativité, nous abordons le comportement créatif des managers en intégrant le modèle BAM (behavioral agency model) et la théorie des capacités dynamiques. L'objectif de notre modèle théorique est d'expliquer en quoi le comportement créatif des managers devant décider d’importantes décisions stratégiques pourrait être considéré comme dynamique et évoluer avec le temps. Concernant la créativité de l'équipe virtuelle, nous avons examiné les déterminants de la créativité. Nous avons constaté que l’approche par les TMS est fructueuse pour la compréhension de la créativité de l'équipe virtuelle. Nos résultats apportent une contribution à la fois à la littérature sur la créativité et à celle concernant les équipes virtuelles et fournissent d'importantes implications managériales pour les équipes virtuelles.Dans l'ensemble, nos recherches sur la créativité individuelle sont également utiles pour les membres de l'équipe virtuelle alors considérés au niveau individuel et l’étude du comportement créatif des managers pourrait aussi s’appliquer aux managers d’équipes virtuelles. Ces quatre articles permettent (1) de fournir une vision globale de la créativité des employés en proposant l'approche par le fit; (2) d’examiner les relations précises entre la prise de risque et la créativité des employés; (3) d’étendre la théorie de la créativité en intégrant le modèle BAM et la théorie des capacités dynamiques afin de considérer la créativité comme dynamique; (4) et de révéler le rôle important du TMS pour la créativité de l'équipe virtuelle. / Many organizations have relied on creativity to outclass their competitors and the knowledge of how to support creativity has been critical. Generally, creativity could be derived from individuals or a group of individuals working together. Hence, in this thesis, we aim to provide a better understanding on how to facilitate creativity at both individual and team levels. Precisely, for the team level, we focus on virtual team creativity which has been under-researched and challenging to discover. The four articles in this dissertation aim to provide a better understanding and identify the determinants of both individual and virtual team creativity. We have reviewed individual creativity literature to extend the understanding of employee creativity. The review suggests that it is more efficient to consider both individual and contextual factors in order to assess employee creativity. Still, the interactions between individual and contextual factors are varied. Therefore, we suggest considering creativity fit approaches between individual and contextual factors derived from the review and we also provide the comprehensive practices for human resource management. In addition, theoretically, several theorists suggest the close relation between risk-taking and employee creativity whereas very few studies have investigated its relations. The second article confirms that there is a positive relation between risk-taking and employee creativity and also demonstrate that individual and contextual factors from both risk and creativity literature are mutually impacted on risk-taking. Later, based on the close relation between risk and creativity theories, we develop the creative behavior of managers by integrating the behavioral agency model and dynamic capabilities theories. The objective of this theoretical model is to explain how the creative behavior of managers in making an important strategic decision could be viewed as dynamic and evolved over time. For virtual team creativity, we aim to examine the determinants of virtual team creativity which have been recently explored. We found that Transactive Memory Systems, which have been challenging due to their importance with regard to virtual teams, have a positive impact on virtual team creativity. The findings extend both creativity and virtual team literature and provide important practical implications for virtual teams. Overall, the investigation of individual creativity is also useful for virtual team members at an individual level and managers’ creative behavior could also assess the creative behavior of virtual team managers. These four articles could in fact (1) provide the global view of employee creativity by proposing the fit approach; (2) examine the precise relations of risk-taking and employee creativity; (3) extend the creativity theory by integrating BAM and the dynamic capabilities theory to consider creativity as dynamic; (4) and reveal the critical roles of TMS in virtual team creativity.