In this thesis, a stacked double-layer flat plate oscillating heat pipe charged with degassed DI water was designed, fabricated and characterized under different operating conditions (orientation, system or cooling water temperature and heat load). The oscillating heat pipe was designed to dissipate 500 W within a footprint of 170 x 100 mm2. The oscillating heat pipe had a total of 46 channels (23 channels per layer) with a nominal diameter of 2 mm. Tests were performed to characterize the performance of the oscillating heat pipe for (i) axial heat transfer and (ii) as a heat spreader. The stacked oscillating heat pipe showed a distinctive feature in that it overcame the absence of the gravity effect when operated in a horizontal orientation. The thermal performance was found to be greatly dependent on the operational parameters. The oscillating heat pipe was able to dissipate a heat load greater than 500 W without any indication of dry-out. An increase in the cooling water temperature enhanced the performance and was accompanied with an increase in the on/off oscillation ratio. The lowest thermal resistance of 0.06 K/W was achieved at 500 W with a 50℃ cooling water temperature, with a corresponding evaporator heat transfer coefficient of 0.78 W/cm2K. The oscillating heat pipe improved the heat spreading capability when locally heated at the middle and end locations. The thermal performance was enhanced by 27 percent and 21 percent, respectively, when compared to a plain heat spreader. / Thesis / Master of Applied Science (MASc)

LEDs are being developed as the next generation lighting source due to their high efficiency and long life time, with a potential to save $15 billion per year in energy cost by 2020. State of the art LEDs are capable of emitting light at ~115 lm/W and have lifetime over 50,000 hours. It has already surpassed the efficiency of incandescent light sources, and is even comparable to that of fluorescent lamps. Since the total luminous flux generated by a single LED is considerably lower than other light sources, to be competitive the total light output must be increased with higher forward currents and packages of multiple LEDs. However, both of these solutions would increase the junction temperature, which degrades the performance of the LED--as the operating temperature goes up, the light intensity decreases, the lifetime is reduced, and the light color changes. The word "junction" refers to the p-n junction within the LED-chips. Critical to the temperature rise in high powered LED sources is the very large heat flux at the die level (100-500 W/cm2) which must be addressed in order to lower the operating temperature in the die. It is possible to address the spreading requirements of high powered LED die through the use of power electronic substrates for efficient heat dissipation, especially when the die are directly mounted to the power substrate in a chipon- board (COB) architecture. COB is a very attractive technology for packaging power LEDs which can lead improved price competiveness, package integration and thermal performance. In our work high power LED-chips (>1W/die) implementing COB architectures were designed and studied. Substrates for these packaging configurations include two types of power electronic substrates; insulated-metal-substrates (IMS) and direct-bonded-copper (DBC). To lower the operating temperature both the thermal impedance of the dielectric layer and the heat spreading in the copper circuit layers must be studied. In the analysis of our architectures, several lead free solders and thermal interface materials were considered. We start with the analysis of single-chip LED package and extend the result to the multi-chip arrays. The thermal resistance of the system is only a function of geometry and thermal conductivity if temperature-independent properties are used. Thus through finite element analysis (ANSYS) the effect of geometry and thermal conductivity on the thermal resistance was investigated. The drawback of finite element analysis is that many simulations must be conducted whenever the geometry or the thermal conductivity is changed. To bypass same of the computational load, a thermal resistance network was developed. We developed analytical expressions of the thermal resistance, especially focusing on the heat spreading effect at the substrate level. Finally, multi-chip LED arrays were analyzed through finite element analysis and an analytical analysis; where die-spacing is another important factor to determine the junction temperature. With this thermal analysis, critical design considerations were investigated in order to minimize device temperatures and thereby maximizing light output while also maximizing device reliability.

<p dir="ltr"><i>The high heat fluxes generated in electronic devices must be effectively diffused through </i><i>the semiconductor substrate and packaging layers to avoid local, high-temperature “hotspots” </i><i>that govern long-term device reliability. In particular, advanced semiconductor packaging </i><i>trends toward thin form factor products increase the need for understanding and improving </i><i>in-plane conduction heat spreading in anisotropic materials. Furthermore, predicting thermal </i><i>transport in vertical stacks of thinned and bonded die hinges on accurately characterizing </i><i>unknown buried interfacial thermal resistances. The design of semiconductor thermal packaging </i><i>solutions is hence limited by the functionality and accuracy of metrology available </i><i>for thermal properties characterization of engineered anisotropic heat spreading materials </i><i>and buried interfaces. This work focuses on the development of two separate innovative </i><i>metrology techniques for characterizing in-plane thermal properties of both isotropic and </i><i>anisotropic materials, and the measurement of low thermal interfacial resistances embedded </i><i>in stacks of semiconductor substrates.</i></p><p dir="ltr"><i>In the first portion of this thesis, a new measurement technique is developed for characterizing </i><i>the isotropic and anisotropic in-plane thermal properties of thin films and sheets, </i><i>as an extension of the traditional Ångstrom method and other lock-in thermography techniques. </i><i>The measurement leverages non-contact infrared temperature mapping to quantify </i><i>the thermal response to laser-based periodic heating at the center of a suspended thin film </i><i>sample. This novel data extraction method does not require precise knowledge of the boundary </i><i>conditions. To validate the accuracy of this technique, numerical models are developed </i><i>to generate transient temperature profiles for hypothetical anisotropic materials with known </i><i>properties. The resultant temperature profiles are processed through a fitting algorithm to </i><i>extract the in-plane thermal conductivities, without the knowledge of the input properties </i><i>to the forward model. Across a wide range of in-plane thermal conductivities, these results </i><i>agree well with the input values. The limits of accuracy of this technique are identified based </i><i>on the experimental and sample parameters. Further, numerical simulations demonstrate </i><i>the accuracy of this technique for materials with thermal conductivities from 0.1 to 1000 W </i><i>m</i><i>−1 </i><i>K</i><i>−1</i><i>, and material thicknesses ranging from 0.1 to 10 mm. This technique effectively</i> <i>measures anisotropy ratios up to 1000:1. Data from multiple heating frequencies can be </i><i>combined to fit for a single set of thermal properties (independent of frequency), which improves </i><i>measurement sensitivity as the thermal penetration depth varies across frequencies. </i><i>The post-processing algorithm filters out regions within the laser absorber and heat sink to </i><i>eliminate regions in the sample domain with boundary effects. Based on these guidelines, </i><i>experiments demonstrate the accuracy of this measurement technique for a wide range of </i><i>known isotropic and anisotropic heat spreading materials across a thermal conductivity range </i><i>of 0.3 to 700 W m</i><i>−1 </i><i>K</i><i>−1</i><i>, and in-plane anisotropy ratios of 30:1. These steps contribute </i><i>towards standardization of this measurement technique, enabling the development and characterization </i><i>of engineered heat spreading materials with desired anisotropic properties for </i><i>various applications.</i></p><p dir="ltr"><i>The second portion of this thesis focuses on characterization of thermal resistances across </i><i>“buried” interfaces that are challenging to characterize in situ due to their low relative magnitude </i><i>and embedded depth within a material stack. In particular, we target characterization </i><i>of interfaces that are buried deeper than the thermal penetration depth of available transient </i><i>measurement techniques, such as thermoreflectance, but have low thermal resistances </i><i>that prohibit the use of steady-state techniques, such as the reference bar method, due to </i><i>the very high temperature gradients that would be necessary resolve the resistances, among </i><i>other sample preparation challenges. This work develops a technique for the non-destructive </i><i>characterization of such deeply buried interfaces having thermal contact resistances of the </i><i>order of 0.001 cm</i><i>2</i><i>K/W. Two different embodiments of the measurement approach are first </i><i>assessed before down-selecting to a single experimental implementation. The working principle </i><i>for both embodiments includes a combination of non-contact periodic heating and </i><i>thermal sensing to measure the transient temperature response of a two-layer stack of materials </i><i>with a bonded interface of unknown thermal resistance. The approaches aim to </i><i>eliminate the preparation requirement of cutting samples to investigate their temperature in </i><i>cross-section. In the first embodiment, the sample stack is heated periodically at the center </i><i>of the sample, and cooled at the periphery, to create a radial temperature gradient. The </i><i>second embodiment involves generating a one-dimensional temperature gradient across the </i><i>stack by periodic heating of one face and steady cooling of the other face. The corresponding </i><i>ing amplitude and phase delay of the temperature responses are used to fit for the thermal </i><i>interfacial resistance, assuming a time-periodic solution for the heat diffusion equation for </i><i>a system with periodic heating. Numerical models developed for both approaches simulate </i><i>the transient temperature profiles across a two-layer bonded silicon stack of known thermal </i><i>properties, and enable an assessment of both approaches. The one-dimensional (1D) gradient </i><i>approach is found to have higher sensitivity and measurable signal compared to the </i><i>radial spreading approach, at the same mean temperature of the sample. </i></p><p dir="ltr"><i>Based on this 1D gradient concept, an experimental facility is developed, which includes </i><i>a IR-transparent heat sink, laser-based heating, and two IR temperature sensors for noncontact </i><i>temperature measurement of both sides of the sample. The unique IR transparent </i><i>heat sink design allows for simultaneous cooling and non-contact temperature measurement </i><i>of the bottom surface of the sample. An inverse fitting method is developed to extract </i><i>the thermal resistances using the steady periodic temperature amplitude and phase delay </i><i>across the thickness of the material. Thermal data generated using numerical simulations, </i><i>along with the data fitting method, is first leveraged to validate the extracted thermal resistance </i><i>values for two-layer material systems with an bonded interface, as well as for the </i><i>thermal conductivity measurement of bulk materials without an interface. The data extraction </i><i>process is shown to accurately extract thermal contact resistances on the order of </i><i>0.0001 cm</i><i>2</i><i>K/W in silicon-based packages for interfaces that are a few millimeters from the </i><i>exposed surface. For bulk materials, this technique demonstrates accuracy in extracting </i><i>the thermal conductivity of a wide range of materials ranging from thermal insulators to </i><i>highly conductive materials, spanning a range of 0.1 to 2000 W m</i><i>−1 </i><i>K</i><i>−1</i><i>. Physical measurements </i><i>of thermal conductivity of bulk silicon nitride and zinc oxide agree well with expected </i><i>reference values, and these measurements also align well with data from independently performed </i><i>experiments on the same materials using an established ASTM D5470 standard, </i><i>thereby validating this new measurement technique experimentally. Two-layer dry-contact </i><i>stacks of these two materials demonstrate the extraction of the thermal resistance across </i><i>interfaces buried up to 2 mm from the exposed surface. This work contributes toward standardization </i><i>of this technique for measurement of thermal resistances with low magnitudes </i><i>and buried depths, which are commonly found in modern electronic packages, ranging from </i><i>near-junction epitaxial semiconductor films to interconnect layers in emerging die-to-die and </i><i>wafer hybrid bonding technologies.</i></p><p dir="ltr"><i>Ultimately, these measurement techniques of in-plane thermal conductivity measurement </i><i>of anisotropic materials and the interfacial contact resistance measurements across buried </i><i>interfaces offer an important contribution to the area of thermal metrology, and advance the </i><i>field of next-generation semiconductor packaging.</i></p>