Thesis(M.S.)--Auburn University, 2005. / Abstract. Vita. Includes bibliographic references.

With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any number of these computing elements. However, one of the major challenges for constructing such a platform is the lack of a standardized framework under which an application’s computational task and data can be easily and effectively managed amongst the computing elements. In this thesis work such a framework is developed based on OpenCL (Open Computing Language). An OpenCL API and run time framework, called O4F, was implemented to incorporate FPGAs in a platform with CPUs and GPUs under the OpenCL framework. O4F help explore the possibility of using OpenCL as the framework to incorporate FPGAs with CPUs and GPUs. This thesis details the findings of this first-generation implementation and provides recommendations for future work.

With the availability of multi-core processors, high capacity FPGAs, and GPUs, a heterogeneous platform with tremendous raw computing capacity can be constructed consisting of any number of these computing elements. However, one of the major challenges for constructing such a platform is the lack of a standardized framework under which an application’s computational task and data can be easily and effectively managed amongst the computing elements. In this thesis work such a framework is developed based on OpenCL (Open Computing Language). An OpenCL API and run time framework, called O4F, was implemented to incorporate FPGAs in a platform with CPUs and GPUs under the OpenCL framework. O4F help explore the possibility of using OpenCL as the framework to incorporate FPGAs with CPUs and GPUs. This thesis details the findings of this first-generation implementation and provides recommendations for future work.

Thesis (M.S. in Computer Science)--Naval Postgraduate School, March 2005. / Thesis Advisor(s): Gurminder Singh, Su Wen. Includes bibliographical references (p. 81). Also available online.

The Boolean satisfiability (SAT) problem is central to many applications involving the verification and optimization of digital systems. These combinatorial problems are typically solved by using a decision-based approach, however the lengthy compute time of SAT can make it prohibitively impractical for some applications. We discuss how the underlying physical characteristics of various technologies affect the practicality of SAT solvers. Power dissipation and other physical limitations are increasingly restricting the improvement in performance of conventional software on CPUs. We use heterogeneous computing to maximize the strengths of different underlying technologies as well as different computing architectures. In this thesis, we present a custom hardware architecture for accelerating the common computation within a SAT solver. Algorithms and data structures must be fundamentally redesigned in order to maximize the strengths of customized computing. Generalizable optimizations are proposed to maximize the throughput, minimize communication latencies, and aggressively compact the memory. We tightly integrate as well as jointly optimize the hardware accelerator and the software host. Our fully implemented system is significantly faster than pure software on real-life SAT problems. Due to our insights and optimizations, we are able to benchmark SAT in uncharted territory. / Thesis / Doctor of Philosophy (PhD)

Heterogeneous computer systems are ubiquitous in all areas of computing, from mobile to high-performance computing. They promise to deliver increased performance at lower energy cost than purely homogeneous, CPU-based systems. In recent years GPU-based heterogeneous systems have become increasingly popular. They combine a programmable GPU with a multi-core CPU. GPUs have become flexible enough to not only handle graphics workloads but also various kinds of general-purpose algorithms. They are thus used as a coprocessor or accelerator alongside the CPU. Developing applications for GPU-based heterogeneous systems involves several challenges. Firstly, not all algorithms are equally suited for GPU computing. It is thus important to carefully map the tasks of an application to the most suitable processor in a system. Secondly, current frameworks for heterogeneous computing, such as OpenCL, are low-level, requiring a thorough understanding of the hardware by the programmer. This high barrier to entry could be lowered by automatically generating and tuning this code from a high-level and thus more user-friendly programming language. Both challenges are addressed in this thesis. For the task mapping problem a machine learning-based approach is presented in this thesis. It combines static features of the program code with runtime information on input sizes to predict the optimal mapping of OpenCL kernels. This approach is further extended to also take contention on the GPU into account. Both methods are able to outperform competing mapping approaches by a significant margin. Furthermore, this thesis develops a method for targeting GPU-based heterogeneous systems from OpenMP, a directive-based framework for parallel computing. OpenMP programs are translated to OpenCL and optimized for GPU performance. At runtime a predictive model decides whether to execute the original OpenMP code on the CPU or the generated OpenCL code on the GPU. This approach is shown to outperform both a competing approach as well as hand-tuned code.

In today's heterogeneous computing environment, a wide variety of computing devices with varying capabilities need to access information in the network. Existing network is not able to differentiate the different device capabilities, and indiscriminatingly send information to the end-devices, without regard to the ability of the end-devices to use the information. The goal of a device-aware network is to match the capability of the end-devices to the information delivered, thereby optimizing the network resource usage. In the battlefield, all resources - including time, network bandwidth and battery capacity - are very limited. A device-aware network avoids the waste that happens in current, device-ignorant networks. By eliminating unusable traffic, a device-aware network reduces the time the end-devices spend receiving extraneous information, and thus saves time and conserves battery-life. In this thesis, we evaluated two potential DAN architectures, Proxy-based and Router-based approaches, based on the key requirements we identified. To demonstrate the viability of DAN, we built a prototype using a hybrid of the two architectures. The key elements of our prototype include a DAN browser, a DAN Lookup Server and DAN Processing Unit (DPU). We have demonstrated how our architecture can enhance the overall network utility by ensuring that only appropriate content is delivered to the end-devices.

by Fu Chengpeng. / Thesis (Ph.D.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (p. 102-119). / Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web. / Mode of access: World Wide Web. / Abstracts in English and Chinese.

No description available.

Ip, Yin Ki. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2007. / Includes bibliographical references (leaves 96-102). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgement --- p.iv / Chapter 1 --- Introduction --- p.1 / Chapter 2 --- Background Study --- p.6 / Chapter 2.1 --- DTN Reference Implementation Model --- p.7 / Chapter 2.2 --- DTN Applications --- p.9 / Chapter 2.3 --- Multiple-copy Routing Strategies --- p.11 / Chapter 2.4 --- Buffer Management Strategies --- p.12 / Chapter 2.5 --- Performance Modeling of Multiple-copy Routing --- p.14 / Chapter 2.6 --- Conclusion on Background Study --- p.18 / Chapter 3 --- DTN with Resource Constraints --- p.20 / Chapter 3.1 --- Introduction --- p.20 / Chapter 3.2 --- Related Work --- p.21 / Chapter 3.3 --- "System Model, Replication, Forwarding and Buffer Management Strategies" --- p.22 / Chapter 3.4 --- Performance Evaluation --- p.29 / Chapter 3.4.1 --- Analysis on single-message-delivery with unlimited network resource --- p.29 / Chapter 3.4.2 --- Simulation study on multi-message-delivery with limited resource constraint --- p.34 / Chapter 3.5 --- Conclusion on DTN with Resource Constraints --- p.39 / Chapter 4 --- Multiple-copy Routing in DTN with Heteroge- neous Node Types --- p.41 / Chapter 4.1 --- Introduction --- p.41 / Chapter 4.2 --- Related Work --- p.44 / Chapter 4.3 --- System Model --- p.44 / Chapter 4.4 --- Performance Modeling --- p.46 / Chapter 4.4.1 --- Continuous Time Markov Chain (CTMC) Model --- p.46 / Chapter 4.4.2 --- Fluid Flow Approximation (FFA) --- p.53 / Chapter 4.5 --- Conclusion on DTN with Node Heterogeneity --- p.73 / Chapter 5 --- Conclusion and Future Work --- p.75 / Chapter A --- Random Direction Mobility Model --- p.78 / Chapter A.1 --- Mean Inter-encounter Interval --- p.79 / Chapter A.2 --- Inter-encounter Interval Distribution --- p.86 / Chapter A.3 --- Concluding Remarks --- p.88 / Chapter B --- Additional Results by Fluid Flow Approximation and Moment Closure Methods --- p.92 / Bibliography --- p.96