This thesis explores the use of active inductors as a compact alternative to the bulky passive spiral structures in high-speed I/O circuits. A newly proposed PMOS-based topology is introduced and used in active-inductor terminations. The 1st prototype design fabricated in a 90-nm CMOS process consists of an output driver using active-inductor terminations to provide channel equalization and output impedance matching. From measurement results, the use of active inductors in the termination, as compared to when the active inductor is disabled, increases the vertical eye opening in the receiver side by a factor of two and reduces the jitterp-p by 30% of the transmitted 10 Gb/s (2³¹-1) pseudo-random binary sequence pattern, over a 6-inch FR4 channel. An output impedance matching with S₂₂ less than -10 dB over a bandwidth of 20 GHz is achieved. The pair of active-inductor terminations occupies 17×25 µm² and has a low overhead power consumption of 0.8 mW. In the 2nd prototype design, a 4-stage output buffer with active-inductor loads is designed and implemented in a 65-nm CMOS process. Simulation results verify that when operating at 31.25 Gb/s, the output eye of the active-inductor load buffer compares favorably with that of the passive-inductor load buffer. For a similar eye-height and 78% less timing jitter the active-inductor load design’s speed (31.25 Gb/s) is 25% faster than the passive-resistor load design (25 Gb/s). The active-inductor load output buffer achieves comparable performance in terms of speed, power, and output swing with other reported designs using passive inductors. Its total area is 135×30 µm² (including three differential active inductors) which is comparable to the size of a single passive spiral inductor having a 0.5~1 nH inductance.

This thesis explores the use of active inductors as a compact alternative to the bulky passive spiral structures in high-speed I/O circuits. A newly proposed PMOS-based topology is introduced and used in active-inductor terminations. The 1st prototype design fabricated in a 90-nm CMOS process consists of an output driver using active-inductor terminations to provide channel equalization and output impedance matching. From measurement results, the use of active inductors in the termination, as compared to when the active inductor is disabled, increases the vertical eye opening in the receiver side by a factor of two and reduces the jitterp-p by 30% of the transmitted 10 Gb/s (2³¹-1) pseudo-random binary sequence pattern, over a 6-inch FR4 channel. An output impedance matching with S₂₂ less than -10 dB over a bandwidth of 20 GHz is achieved. The pair of active-inductor terminations occupies 17×25 µm² and has a low overhead power consumption of 0.8 mW. In the 2nd prototype design, a 4-stage output buffer with active-inductor loads is designed and implemented in a 65-nm CMOS process. Simulation results verify that when operating at 31.25 Gb/s, the output eye of the active-inductor load buffer compares favorably with that of the passive-inductor load buffer. For a similar eye-height and 78% less timing jitter the active-inductor load design’s speed (31.25 Gb/s) is 25% faster than the passive-resistor load design (25 Gb/s). The active-inductor load output buffer achieves comparable performance in terms of speed, power, and output swing with other reported designs using passive inductors. Its total area is 135×30 µm² (including three differential active inductors) which is comparable to the size of a single passive spiral inductor having a 0.5~1 nH inductance.

This thesis explores the use of active inductors as a compact alternative to the bulky passive spiral structures in high-speed I/O circuits. A newly proposed PMOS-based topology is introduced and used in active-inductor terminations. The 1st prototype design fabricated in a 90-nm CMOS process consists of an output driver using active-inductor terminations to provide channel equalization and output impedance matching. From measurement results, the use of active inductors in the termination, as compared to when the active inductor is disabled, increases the vertical eye opening in the receiver side by a factor of two and reduces the jitterp-p by 30% of the transmitted 10 Gb/s (2³¹-1) pseudo-random binary sequence pattern, over a 6-inch FR4 channel. An output impedance matching with S₂₂ less than -10 dB over a bandwidth of 20 GHz is achieved. The pair of active-inductor terminations occupies 17×25 µm² and has a low overhead power consumption of 0.8 mW. In the 2nd prototype design, a 4-stage output buffer with active-inductor loads is designed and implemented in a 65-nm CMOS process. Simulation results verify that when operating at 31.25 Gb/s, the output eye of the active-inductor load buffer compares favorably with that of the passive-inductor load buffer. For a similar eye-height and 78% less timing jitter the active-inductor load design’s speed (31.25 Gb/s) is 25% faster than the passive-resistor load design (25 Gb/s). The active-inductor load output buffer achieves comparable performance in terms of speed, power, and output swing with other reported designs using passive inductors. Its total area is 135×30 µm² (including three differential active inductors) which is comparable to the size of a single passive spiral inductor having a 0.5~1 nH inductance. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

The growing demand for high performance systems in modern computing technology drives the development of advanced and high speed designs in I/O structures. Due to their data rate and architecture, however, testing of the high speed serial interfaces becomes more expensive when using conventional test methods. In order to alleviate the test cost issue, a loopback test scheme has been widely adopted. To assess the margin of the signal eye in the loopback configuration, the eye margin is purposely reduced by additional devices on the loopback path or using design for testability (DFT) features such as timing and voltage margining. Although the loopback test scheme successfully reduces the test cost by decoupling the dependency of external test equipment, it has robustness issues such as a fault masking issue and a non-ideality problem of margining circuits. The focus of this dissertation is to propose new methods to resolve the known issues in the loopback test mode. The fault masking issue in a loopback pair of analog to digital and digital to analog converters (ADC and DAC) which can be found in pulse amplitude modulation (PAM) signaling schemes is resolved using a proposed algorithm which separates the characteristics of the ADC and the DAC from a combined loopback response. The non-ideality problem of margining circuit is resolved using a proposed method which utilizes a random jitter injection technique. Using the injected random jitter, the jitter distribution is sampled by undersampling and margining, which provides the nonlinearity information using the proposed algorithm. Since the proposed method requires a random jitter source on the load board, an alternative solution is proposed which uses an intrinsic jitter profile and a sliding window search algorithm to characterize the nonlinearities. The sliding search algorithm was implemented in a low cost high volume manufacturing (HVM) tester to assess feasibility and validity of the proposed technique. The proposed methods are compatible with the existing loopback test scheme and require a minimal area and design overhead, hence they provide cost effective ways to enhance the robustness of the loopback test scheme. / text

Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, has leveraged equalization techniques to operate reliably on band-limited channels at additional power and area complexity. High-bandwidth inter-chip optical interconnect architectures have the potential to address this increasing I/O bandwidth. Considering future tera-scale systems, power dissipation of the high-speed I/O link becomes a significant concern. This work presents a design flow for the power optimization and comparison of high-speed electrical and optical links at a given data rate and channel type in 90 nm and 45 nm CMOS technologies. The electrical I/O design framework combines statistical link analysis techniques, which are used to determine the link margins at a given bit-error rate (BER), with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate and process node for three different channels. The transmitter output swing is scaled to operate the link at optimal power efficiency. Under consideration for optical links are a near-term architecture consisting of discrete vertical-cavity surface-emitting lasers (VCSEL) with p-i-n photodetectors (PD) and three long-term integrated photonic architectures that use waveguide metal-semiconductor-metal (MSM) photodetectors and either electro-absorption modulator (EAM), ring resonator modulator (RRM), or Mach-Zehnder modulator (MZM) sources. The normalized transistor parameters are applied to jointly optimize the transmitter and receiver circuitry to minimize total optical link power dissipation for a specified data rate and process technology at a given BER. Analysis results shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing, allows electrical links to achieve excellent power efficiency at high data rates. While the high-loss channel is primarily limited by severe frequency dependent losses to 12 Gb/s, the critical timing path of the first tap of the decision feedback equalizer (DFE) limits the operation of low-loss channels above 20 Gb/s. Among the optical links, the VCSEL-based link is limited by its bandwidth and maximum power levels to a data rate of 24 Gb/s whereas EAM and RRM are both attractive integrated photonic technologies capable of scaling data rates past 30 Gb/s achieving excellent power efficiency in the 45 nm node and are primarily limited by coupling and device insertion losses. While MZM offers robust operation due to its wide optical bandwidth, significant improvements in power efficiency must be achieved to become applicable for high density applications.