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This project analyzes the validity of theoretical models used to predict the duration (hold time) for which a halon-replacement suppression agent will remain within a protected enclosure. Two current models and one new formulation are investigated; the sharp descending interface model (as applied in NFPA 2001, Annex C), the wide descending interface model (implemented in ISO 14520.1, Annex E), and the thick descending interface model (introduced herein). The thick interface model develops the characteristic thickness as an additional input parameter. Experimental data from 34 full-scale tests designed to characterize the discharge and draining dynamics of seven clean extinguishing agents (CEA) is used to assess model validity. For purposes of model validation the characteristic thickness is regressed from the experimental data although further work may be required to establish the independence of this parameter to other system design and environmental variables. Results show that the wide and sharp interface models' validity is highly sensitive to the threshold of agent concentration decay being modeled; whereas the thick interface prediction method demonstrates increased robustness at any modeled threshold. When the hold time is defined as a 15% decay in agent concentration, experimentally obtained hold time values are roughly 10% shorter than sharp interface predictions, 60% longer than wide interface predictions, and 30% longer than the thick interface model predicts.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

Com o desenvolvimento da tecnologia CMOS, os circuitos estão ficando cada vez mais sujeitos a variabilidade no processo de fabricação. Variações estatísticas de processo são um ponto crítico para estratégias de projeto de circuitos para garantir um yield alto em tecnologias sub-100nm. Neste trabalho apresentamos uma técnica de medida on-chip para caracterizar violações de tempo de hold de flip-flops em caminhos lógicos curtos, que são geradas por incertezas de borda de relógio em projetos síncronos. Usando um circuito programável preciso de geração de skew de relógio, uma resolução de medida de ~1ps é alcançada para emular condições de corrida. Variações estatísticas de violações de tempo de hold são medidas em tecnologias CMOS de 130nm e 90nm para diversas configurações de circuitos, e também para diferentes condições de temperatura e Vdd. Essas violações são um ponto crítico em projetos grandes com milhares de caminhos curtos, pois se apenas um desses caminhos falhar, todo o circuito não vai funcionar em qualquer freqüência. Usando os resultados medidos, a variabilidade é dividida entre sistemática e randômica residual usando métodos matemáticos. Testes de normalidade são aplicados a estes dados para verificar de eles são Gaussianos normais ou não. A probabilidade de violações de tempo de hold considerando nossos resultados medidos e skews de relógio típicos é calculada, mostrando que o problema de violações de tempo de hold aumenta com o avanço da tecnologia. Finalmente, um algoritmo para proteger circuitos digitais contra violações de tempo de hold em caminhos curtos é apresentado. / With the shrinking of CMOS technology, the circuits are more and more subject to variability in the fabrication process. Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm and 90nm lowpower CMOS technology for various register-to-register configurations, and also different conditions of temperature and Vdd. These violations are a critical issue in large designs with thousands of short paths, as if only one of these fails, the whole circuit will not work at any frequency. Using the measured results, the variability is divided between systematic and random residual using mathematical methods. Normality tests are applied to this data to check if they are normal Gaussians or not. The probability of hold time violations considering our measured data and typical clock skews is calculated, showing that the problem of hold time violations is increasing with technologic advances. Finally, an algorithm to protect digital circuits against hold time violations in short paths is presented.

L’Inconel 718 est un superalliage base nickel largement utilisé par les motoristes tels Safran Aircraft Engines pour l’élaboration des disques de turbine. Après forgeage des disques, un traitement de vieillissement appelé « Direct Aged » est appliqué. En service, le régime de croisière représente un temps de maintien sous chargement constant pour les disques. Bien que pas complètement compris, il est largement admis qu’un temps de maintien dans un cycle de fatigue a un effet néfaste sur le comportement en fissuration de l’Inconel 718 ainsi que d’autres superalliages. Cette étude porte donc sur la fissuration en fatigue-fluage dans l’Inconel 718 DA à 550°C et 650°C. Des essais sont menés pour des temps de maintien allant jusqu’à 1h. Des développements de la méthode de suivi de fissure par mesure de potentiel (DCPD) ont permis d’identifier la décharge-recharge (contribution de fatigue) d’un cycle de fatigue-fluage comme la partie la plus néfaste du cycle. L’application d’un temps de maintien amplifie cette contribution. Le temps de maintien induit également des fronts de fissure extrêmement courbes et tortueux, contrairement à de la fatigue pure. Une stratégie numérique a été développée, couplant la simulation 3D de la propagation et la méthode dite DCPD, permettant de réaliser des « essais numériques ». La propagation de fronts courbes et tortueux est simulée. Il a été démontré que le comportement en propagation est directement lié à la forme du front de fissure et son évolution. Des essais complexes ont été menés, sous vide, ou impliquant des surcharges. Lorsque l’effet du temps de maintien est annihilé, les morphologies complexes des fronts disparaissent. Elles sont alors associées à une inhibition locale de l’effet endommageant de l’environnement due à la plasticité et aux vitesses de déformation locales. Tous les essais présentés sont analysés en considérant l’effet de la vitesse de déformation locale qui influe largement le comportement en fissuration de l’Inconel 718. / Inconel 718 is a nickel-based superalloy widely used by aeroengines manufacturers like Safran Aircraft Engine to manufacture turbine disks. After forging, disks are given an ageing treatment called “Direct Aged”. In service, during cruise, these critical components handle hold-time periods at constant loading. It is well known, although not fully understood, that hold-time increases crack growth rates (CGR) in Inconel 718 as well as others superalloys. Therefore, this study focuses on crack propagation under hold-time conditions in DA Inconel 718, at 550°C and 650°C. Experiments were carried out for different hold-times, up to 1h. Developments on the crack monitoring technique (DCPD) led to the conclusion that the most damaging part of the cycle is load-reversal (fatigue contribution). This contribution is enhanced by the hold-time period. Holdtime leads to dramatically curved and tortuous crack front, contrary to pure fatigue cycles. A numerical framework was developed, combining crack growth and DCPD simulations, so that “numerical tests” can be carried out. Using this method, crack growth simulations were performed from curved and tortuous, experimentally reproduced, crack front. It was concluded that increased crack CGR under hold-time conditions are closely related to the crack front morphology and its evolution during propagation. More complex tests, with overloads or under vacuum, were carried out. When the hold-time effect is inhibited, complex morphologies vanish. Such morphologies were associated to local inhibition of the environmental damaging effect due to local high plastic strain and strain rates. The large variety of experiments, presented in this study, was then successfully analyzed considering the effect of local strain rates which greatly influence the crack growth behavior of Inconel 718.

GKN Aerospace AB, Sweden (GAS) is one of the leading companies taking up the charge in manufacturing components using Additive Manufacturing(ed) (AM) techniques in the aerospace sector. They are a hub of engineering and they are a supplier of engine and engine components to the world’s leading aero-engine manufacturers, and airframes to civil and military aircraft manufacturers. A phenomenon that is of interest to designers at GAS is the effects of dwell times on high temperature fatigue, especially how this phenomenon affects the fatigue properties of Laser Powder Bed Fusion (LPBF) Inconel 718 (IN718). IN718 is a versatile alloy that can be used at relatively high temperatures and has excellent weldability and is one of the newer materials replacing expensive materials such as Titanium (and its alloys) in the aerospace industry. The aerospace industry has been pushing for an increase in parts manufactured using AM processes because of the advantage the AM process grants to the production process, however a new manufacturing process for an industry needs to be studied and researched from a failure perspective, i.e. the prominent mode of failure for components manufactured using AM and the underlying factors influencing the failure mechanism must be studied. This thesis explores a solution to predict the life of components based on experimental crack propagation tests wherein the test specimens were subjected to the phenomenon mentioned above. A literature survey was conducted researching ways to model this phenomenon and the factors affecting it. The methods found in the literature survey were far too complex to model for the purposes of this thesis, additionally the methods described in the literature were empirical methods describing the phenomenon, rather than a fundamental study of factors causing the phenomenon and ways to model their influence on the life of the component. Hence, a simple method based on the Palmgren-Miner linear damage summation rule which was coded in the form of a FORTRAN code was utilized to compute the life of the components. Software runs predicting life of physical experiments were conducted and inferences about the predictive method were drawn. The limitations of this method were understood and possible solutions were explored, based on which conclusions were drawn regarding the method’s efficacy in predicting the life of the specimens that underwent dwell loading during fatigue cycling. Finally, the method was applied to a case study to understand the effectiveness of the method. / GKN Aerospace AB, Sverige (GAS) är ett av de ledande företagen som tar upp kampen vid tillverkning av komponenter med hjälp av additiv tillverkning (AM) inom flyg- och rymdsektorn. De är ett nav för ingenjörskonst och de är en leverantör av motorer och motorkomponenter till världens ledande tillverkare av flygmotorer, och civila och militära flygplanstillverkare. Ett fenomen som är av intresse för designers på GAS är effekterna av uppehållstider på högtemperaturutmattning, särskilt hur detta fenomen påverkar utmattningen egenskaper hos Laser Powder Bed Fusion (LPBF) Inconel 718 (IN718). IN718 är en mångsidig legering som kan användas vid relativt höga temperaturer och har utmärkt svetsbarhet och är ett av de nyare materialen som ersätter dyra material såsom titan (och dess legeringar) inom flygindustrin. Flygindustrin har drivit på för en ökning av delar som tillverkas med additiva tillverkningsprocesser på grund av den fördel som tillverkningsprocessen ger en ny tillverkningsprocess för en industri behöver dock studeras och forskat ur ett misslyckandeperspektiv, dvs. det framträdande sättet att misslyckas för komponenter som tillverkats med hjälp av additiv tillverkning och de bakomliggande faktorer som mekanismen måste studeras. Denna avhandling utforskar en lösning för att förutsäga livslängden för komponenter baserat på experimentella sprickutbredningstester där provexemplaren utsattes för fenomenet som nämns ovan. En litteraturstudie genomfördes för att undersöka olika sätt att modellera detta fenomenet och de faktorer som påverkar det. Metoderna som framkom i litteraturstudien var alldeles för komplexa för att modellera för denna avhandling, dessutom är metoderna som beskrivits i litteraturen var empiriska metoder som beskriver fenomenet, snarare än en grundläggande studie av de faktorer som orsakar fenomenet och sätt att modellera deras inverkan på komponentens livslängd. Därav en enkel metod baserad på Palmgren-Miners linjära skadesummeringsregel som kodades i form av en FORTRAN-kod användes för att beräkna livslängden för komponenterna. Programvarukörningar som förutspådde livslängden för fysiska experiment genomfördes och slutsatser om den prediktiva metoden drogs. Begränsningarna med denna metod förstods och möjliga lösningar utforskades. Som låg till grund för de slutsatser som drogs om metodens effektivitet när det gäller att förutsäga livslängden för de prover som genomgick uppehållsbelastning underutmattningscykling. Slutligen tillämpades metoden på en fallstudie för att förstå effektiviteten avmetod.