Economic Value Added ¡]EVA¡^to be a business performace indicator popularly. It surveys business¡¦ ability of value creation through tranditional accounting net income and capital opportunity cost. In this study, I focus on IC Design industries¡¦ performance by EVA and use ten years data to examine it. The study purposes as below, A. Does Taiwan IC Design Industry owns ability of value creation for share owners ? B. Find out the factors of Taiwan IC Design Industry¡¦s performance. C. Comment on Taiwan IC Design Industry¡¦s performance in various sub-industries D. Does Taiwan IC Design Industry exist variation in various sub-industries ? E. Find out which sub-industry owns the best efficiency and the lowest volatility in the meanwhile. F. Find out the factors of Taiwan IC Design Industry¡¦s ability of value creation. The study finding as below, A. The standard deviation and quartile deviation of Taiwan IC Design Industry are uniformity and it is implying that the normal distribution and probability distribution are similar. B. About 80% of EVA-Spread of Taiwan IC Design companies are positive, it implies that the ability of value creation of Taiwan IC Design Industry is very well. C. According to evidence-based data, the WACC of Taiwan IC Design Industry is influenced by the cost of equity capital. D. The ROIC of Taiwan IC Design Industry is influenced by Taiwan Semi-conductor Inductry¡¦s ROIC and the real GDP growth rate of Hongkong, China and South Korea. E. The capital turnover of Taiwan IC Design Industry does not link with the ROIC of Taiwan IC Design Industry. F. According to evidence-based data, the variation is exist between Taiwan IC Design Sub-industries. G. The result of regression analysis that past years Invested Capital Growth Rate of sub-industries to be independent variable and EVA-Spreads to be dependent variable implys that the EVA-Spread of Taiwan IC Design Industry is not effected by Invested Capital Growth Rate, then we know that Invested Capital is not the main factor of value creation of Taiwan IC Design Industry. H. The Capital Turnover Rate and the Return Rate of EBIT is the main factors of ROIC, they effected the sub-industries by different levels.

Abstract The developing trend toward the integreation of many function in application market of semiconductor, makes the original business model of IC design industry to change. From open structure (named ¡§Wintel¡¨ structure) till today, what we can see it shows as transition stage. It will be end in the situation the all devices can interlink to each other. All of us don¡¦t know how long we will overcome this transition stage. But it really challenges the orginal business model of IC design industry. The business model of IC design industry changes along with the changing in product application market. In this study, we do analysis of IC design industry¡¦s business model by four dimensions¡Xmarket strategies, capabilities of technology, the types of organization, financial resources. We will discuss the differents between Taiwan and American IC design industry In market strategy dimension, there are more and more difficults to distinguish between past strategy model including niche and volume strategies. Because the revolution of electronics application market, the better ways for Taiwan IC design industry to develop its market strategy are depending on capability focusing and the capture of market demend. When mentioning about the IC design skill, Taiwan IC design industry can choose several ways to cumulate its design capabilities according to the market strategy it chose. About types of the organization, the combination of fabless and fabless is the trend. Also 1¡¦st tier IDM will be the key roles who dominate the future IC industry. More than all, fabless who belong to system assembly factory or fabless who belong to foundry will be the mainstream in the IC industry and in electronics application market, too. Depending on what kinds of organzation IC design companies chose, it will affect the ability when they rising money. These four factors interaction built the business model of the Taiwan IC design industry.

Future high-capacity wireless communications will extensively use the broad bands still available millimeter-wave frequencies. Channels with bandwidth broader than those in use today will guarantee enhanced data-rate and reduced latency performance. The recent progress of integrated-circuit semiconductor technologies finally allowed the design of reliable electronics operating at millimeter-wave frequencies. On top, advanced Fully Depleted Silicon On Insulator (FD-SOI) Complementary Metal Oxide Semiconductor (CMOS) and Silicon Germanium (SiGe) Bipolar CMOS (BiCMOS) processes enabled to co-integrate large digital blocks with frontends operating at tens or hundreds of GHz. The current under-deployment fifth-generation mobile-communication standard (5G) takes advantage of these advancements, massively exploiting the frequency bands from 24 GHz to 100 GHz. Furthermore, besides enlarging the channel bandwidth, improvements of the signal-to-noise power ratio (SNR) at the receiver input, combined with Multiple-Input Multiple-Output (MIMO) techniques provide an additional boost to the communication data-rate. Both approaches require arrays of antennas, plus electronic beam-steering which becomes essential in the case of moving transmitting-receiving pairs. Finally, social, economic, historical, and technological trends indicate that future wireless standards will require data-rates, latencies, and density of served users per square kilometer well beyond those offered by the 5G. Envisioned to be deployed towards the end of this decade, the six mobile communication standard (6G) will win future challenges thanks to the very ultra-broad bands available from 100 GHz until the tens of THz. Basic research is hence needed to address the open challenges necessary to reach the goals of future wireless communication systems, such as bandwidth and frequency operation factor-10 increase or power consumption reduction against the actual state of the art. This Habilitation thesis proposes circuit theory and concepts up to feasibility study of circuit implementation and experimental characterization in the laboratory of transceiver electronics for future high-capacity communications useful for the knowledge gain necessary for the conception of future communication systems. In detail, basic scientific research to understand the operation of millimeter-wave communication circuits implemented in 22 nm FD-SOI CMOS and 130 nm SiGe BiCMOS technologies has been performed.

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.

According to the research of the Taiwan Semiconductor Industry Association in 2004 , IC design in Taiwan is becoming the second major clustering centre after America. IC design house seems to be the upcoming star in Taiwan semiconductor industry, by its highly brainstorming to create higher additional value, it is also the next leading role in hi-tech industry in Taiwan.To IC design house, the quality of employees is the key of competitiveness, therefore, only dependent on the staff's constant research and innovation, could occupy a space on the competitive market, so the reserch of management of professional human resources in IC design house seems even more important. This study adopts the in-deep interview of qualitative reserch, including six RD engineers, four product engineers and five human resources personnel as the research objects.The main purpose is to understand what the employees truely demand in IC design house? How is the operation of human resource management practice and the expectation to Human Resource Department? How the professional personnel of human resources understand the idea and demand of employees, make a right management system and offer the best welfare measure. Through the interview materials, along with domestic, international documents, the results come out as following: 1. The demand of RD engineers and product engineers learning development opportunity / excellent manager / good working environment / understand the employees demand / limitless creation and innovation / the balance of work and life 2. The expectation of RD engineers and product engineers to Human Resource Department to be intercommunication channel / complete training program / attract and retain outstanding talents / strengthen professional ability more actively 3. The contribution of Human Resource Department of IC design house to Human Resource Managemant Recruit high-quality talent / administration efficiency / salary and welfare policy / incentive system to keep talent / promote innovation ability of employees / complete training program / build a common vision /build a high-quality working environment / intercommunication channel / understand the employees truly need 4. IC Design House Human Resource Management Model (1)recruit and employ: recruit channel: manpower bank/ employee recommendation/ campus recruit / national defence labor recruit procedure: recruit by HR or department director employ characteristic: good team player/ dedicated/ learning spirit employ term: response ability/ professional ability/ communication coordinate ability/ innovation ability (2)salary and benefit: attractive payment/ cash allowance/ meal allowance/ entertainment/ group insurance/ society safety/ retirement plan (3)training and development: e-learning/ invite outside instructor/ lessons by senior employees/ seminar/ training plan evaluation/ training result check and accept (4)performance evaluation: fair/ justice/ team performance/ individual performance (5)labor relations: interaction frequently/ diversified encourage program/ resignation management

Since the emergence of knowledge economy, items discussed in traditional accounting practices seemed not to represent the real value of an enterprise effectively. Thus, the conception of intellectual capital has been proposed. However, current intellectual capital measurement methods have limitations such as confirming causation difficultly, lacking integration sufficiently. The purpose of this dissertation is to propose an effective method and process to evaluate intellectual capital. We collected data from annual reposts of IC (Integrated Circuits) design houses in Taiwan. In basis of indicators and association analysis, strategy map for IC design house can be built. Then we compared the efficiency of intellectual capital for IC design houses. The results showed small scale companies might be more efficient than large scale companies. We also observed that intellectual capital value might not be reflected only through association and efficiency analysis. Then system dynamics was adopted to analyze one case. The side effect and leverage factor that hidden in uni-direction thinking of balanced scorecard were found out. This theme also found out indicators of intellectual capital and dynamic loops for the case. Finally, we suggest the policy to increase intellectual capital value for the case.

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.

abstract: High speed current-steering DACs with high linearity are needed in today's applications such as wired and wireless communications, instrumentation, radar, and other direct digital synthesis (DDS) applications. However, a trade-off exists between the speed and resolution of Nyquist rate current-steering DACs. As the resolution increases, more transistor area is required to meet matching requirements for optimal linearity and thus, the overall speed of the DAC is limited. In this thesis work, a 12-bit current-steering DAC was designed with current sources scaled below the required matching size to decrease the area and increase the overall speed of the DAC. By scaling the current sources, however, errors due to random mismatch between current sources will arise and additional calibration hardware is necessary to ensure 12-bit linearity. This work presents how to implement a self-calibration DAC that works to fix amplitude errors while maintaining a lower overall area. Additionally, the DAC designed in this thesis investigates the implementation feasibility of a data-interleaved architecture. Data interleaving can increase the total bandwidth of the DACs by 2 with an increase in SQNR by an additional 3 dB. The final results show that the calibration method can effectively improve the linearity of the DAC. The DAC is able to run up to 400 MSPS frequencies with a 75 dB SFDR performance and above 87 dB SFDR performance at update rates of 200 MSPS. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

abstract: Digital architectures for data encryption, processing, clock synthesis, data transfer, etc. are susceptible to radiation induced soft errors due to charge collection in complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Radiation hardening by design (RHBD) techniques such as double modular redundancy (DMR) and triple modular redundancy (TMR) are used for error detection and correction respectively in such architectures. Multiple node charge collection (MNCC) causes domain crossing errors (DCE) which can render the redundancy ineffectual. This dissertation describes techniques to ensure DCE mitigation with statistical confidence for various designs. Both sequential and combinatorial logic are separated using these custom and computer aided design (CAD) methodologies. Radiation vulnerability and design overhead are studied on VLSI sub-systems including an advanced encryption standard (AES) which is DCE mitigated using module level coarse separation on a 90-nm process with 99.999% DCE mitigation. A radiation hardened microprocessor (HERMES2) is implemented in both 90-nm and 55-nm technologies with an interleaved separation methodology with 99.99% DCE mitigation while achieving 4.9% increased cell density, 28.5 % reduced routing and 5.6% reduced power dissipation over the module fences implementation. A DMR register-file (RF) is implemented in 55 nm process and used in the HERMES2 microprocessor. The RF array custom design and the decoders APR designed are explored with a focus on design cycle time. Quality of results (QOR) is studied from power, performance, area and reliability (PPAR) perspective to ascertain the improvement over other design techniques. A radiation hardened all-digital multiplying pulsed digital delay line (DDL) is designed for double data rate (DDR2/3) applications for data eye centering during high speed off-chip data transfer. The effect of noise, radiation particle strikes and statistical variation on the designed DDL are studied in detail. The design achieves the best in class 22.4 ps peak-to-peak jitter, 100-850 MHz range at 14 pJ/cycle energy consumption. Vulnerability of the non-hardened design is characterized and portions of the redundant DDL are separated in custom and auto-place and route (APR). Thus, a range of designs for mission critical applications are implemented using methodologies proposed in this work and their potential PPAR benefits explored in detail. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers. / The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.